High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- Nano-Tera: PlaCITUS
Next-generation 4G wireless standards such as the LTE-Advanced require broad-band high-precision analog-to-digital converters (ADCs) capable to cover signal bandwidths up to 100MHz with an effective resolution higher than 10bits. Such data converters are intended to be embedded in a mostly digital system, and this legitimates the adoption of ultra-scaled CMOS technologies from which the digital sub-systems can heavily benefit.
Delta-sigma modulation is usually the preferred choice for wireless communications applications, however, this technique is effective only if a sufficiently large oversampling ratio (OSR) can be employed. So far this limitation has restricted the bandwidth achievable to a few tens of megahertz and the accuracy to about 10-11bits. Modern ultra-scaled CMOS technologies, beyond the 45nm technology node, thanks to lower intrinsic parasitics, allow to target broader bandwidths while maintaining a reasonable OSR and therefore preserving resolution.
The goal of this project is the analysis and design of a discrete-time delta-sigma modulator capable to cover 125MHz signal bandwidth with a resolution of 10bits in a 28nm CMOS. A single-loop third-order loop filter em- ploying a 4-bit quantizer has been identified as the best trade-off between complexity and performance. A fully integrated reference buffer provides the required reference voltages without need for external components. The modulator is operated at a sampling rate of 4GHz with an OSR of 16.