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High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS

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Garamon, one of the massive-MIMO digital receiver designed by the IIP group

Short Description

Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO.

The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available.

The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.

Status: Available

Type: Semester project or Master Thesis
Contact: Jérémy Guichemerre, Thomas Burger


Analog Integrated Circuits (AIC)
Basic knowledge of DACs


10% Familiarizing yourself with TSMC 65nm
70% Design
20% Layout


Mathieu Luisier

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Practical Details


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