View source for High-Speed SAR ADC for next generation wireless communication in 12nm FinFET

[[File:idefix.png|400px|thumb|right|Idefix, our first generation high-speed ADC in GlobalFoundries 22nm SOI technology]]

==Short Description==
Due to the very crowded spectrum at lower frequencies, millimeter waves (mmWave) are to be used for the next generations of wireless communication as they offer wide bands of unused spectrum. However, increasing frequency also means that path loss will become problematic. To overcome this issue, massive multi-antenna (MIMO) technology is widely believe to be the key: a matrix of antenna allows to aim the power in a precise direction, hence concentrating the transmitted power in the direction of the receiver.

As GHz’s of bandwidth are available at higher carrier frequencies, 5G and beyond 5G technologies are expected to enable higher data-rates than previous generation communication. This leads to high-speed requirement for the Analog-to-Digital Converter (ADC) which needs to digitize in the order of 1GS/s. Thanks to high number of independent front-ends, the resolution of the ADCs doesn’t need to be very high, in the order of 8-10b. However, as each antenna of the MIMO array leads to 2 ADCs, converters need to have a low power consumption, to be of low area, and not to rely on any other bulky blocks that cannot be shared.

A first generation of such an ADC has been designed in GlobalFoundries (GF) 22fdx technology. For digital circuits, the advantage of scaling to a smaller node is clear, but this is not always the case for analog blocks. Hence, the work of the project will be to explore the new 12nm FinFET technology 12LP from GlobalFoundries by porting the existing 22nm ADC. Purely analog parts will be redesigned fully and exploration will be done about the speed and driving strength of the logic components of the circuits. If time allows it, some layout will also be done for the most sensitive parts of the ADC.

===Status: Available ===
: Type: Semester project or Master Thesis
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]

===Prerequisites===
: Analog Integrated Circuits (AIC)
: Basic knowledge of  SAR ADCs

===Character===
: 10% Exploring the GF 12LP FinFET technology
: 70% Analog Design
: 20% Layout

===Professor===
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]

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==Detailed Task Description==

===Goals===
===Practical Details===
* '''[[Project Plan]]'''
* '''[[Project Meetings]]'''
* '''[[Design Review]]'''
* '''[[Coding Guidelines]]'''
* '''[[Final Report]]'''
* '''[[Final Presentation]]'''

==Results== 

==Links== 
[[Category:Analog]]
[[Category:Available]]
[[Category:Semester Thesis]]
[[Category:Master Thesis]]
[[Category:Burger]]
[[Category:Analog IC Design]]
[[Category:Telecommunications]]
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