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Information for "High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT"

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Display titleHigh Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
Default sort keyHigh Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
Page length (in bytes)3,248
Page ID650
Page content languageEnglish (en)
Page content modelwikitext
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Page creatorLwu (talk | contribs)
Date of page creation13:28, 20 September 2016
Latest editorMocquard (talk | contribs)
Date of latest edit11:45, 20 August 2021
Total number of edits7
Total number of distinct authors3
Recent number of edits (within past 90 days)1
Recent number of distinct authors1