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(Created page with "thumb|600px|Typical Vernier Delay Line based TDC (Time to Digital Convertor) ==Short Description== Tough frequency synthesize require...")
 
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[[File:Vernier-delay-line-based-TDC.png|thumb|600px|Typical Vernier Delay Line based TDC (Time to Digital Convertor)]]
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[[File:Vernier-delay-line-based-TDC.png|thumb|400px|Typical Vernier Delay Line based TDC (Time to Digital Convertor)]]
 
==Short Description==
 
==Short Description==
Tough frequency synthesize requirement imposed by cellular applications have been a key driver for PLL research in recent years. As the age of cellular internet of things is coming, motivation for designing power efficient PLL (supreme phase noise performance at low power) is getting stronger than ever. Locating at the heart of PLL, VCO does not only determine the phase noise performance of PLL (especially far out part) but also contributes considerably to the total power budget. As the result, stringent design specifications provide considerable incentive for research solely focused on improving the voltage-controlled oscillator (VCO) performance, one of the most challenging aspects of PLL design. The aim of this project is to analyze and build such a power efficient sub-10 mW Digital controlled Oscillator (DCO) for GHz frequency range, to achieve a state-of-art performance, finally leading the way to a low power low jitter Digital PLL.  
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As CMOS process node is progressing towards quantum level, voltage headroom is reduced correspondingly while transistor speed is increased on the other hand. Therefore, it is time to use time, indicating that it is beneficial to incorporate signal information into time domain rather than conventional analog voltage domain. This gives the birth of phase domain Digital PLL and thus the emerging of time domain ADC. Compared with its mature analog counterpart topic (Phase/Frequency Detector+ Charge Pump), concept of ADC is leveraged into DPLL to quantize analog phase /frequency error in time domain. This topic is drawing more and more attention over the past 5 years as seen in numerous top publications and patents. Highly digitally-assisted analog design is the trend for time domain ADC, such as DTC+TDC, Bang-Bang Detector. Following such a trend, the aim of this project is to analyze and build a time domain ADC innovatively so that the in-band jitter contribution of the DPLL could be lower than 500fs while consuming power less than 1 mW.  
  
  

Revision as of 12:29, 20 September 2016

Typical Vernier Delay Line based TDC (Time to Digital Convertor)

Short Description

As CMOS process node is progressing towards quantum level, voltage headroom is reduced correspondingly while transistor speed is increased on the other hand. Therefore, it is time to use time, indicating that it is beneficial to incorporate signal information into time domain rather than conventional analog voltage domain. This gives the birth of phase domain Digital PLL and thus the emerging of time domain ADC. Compared with its mature analog counterpart topic (Phase/Frequency Detector+ Charge Pump), concept of ADC is leveraged into DPLL to quantize analog phase /frequency error in time domain. This topic is drawing more and more attention over the past 5 years as seen in numerous top publications and patents. Highly digitally-assisted analog design is the trend for time domain ADC, such as DTC+TDC, Bang-Bang Detector. Following such a trend, the aim of this project is to analyze and build a time domain ADC innovatively so that the in-band jitter contribution of the DPLL could be lower than 500fs while consuming power less than 1 mW.


Status: Available

Looking for 1-2 Semester students
Contact: Lianbo Wu

Prerequisites

AIC

Character

30% Theory
70% Circuit Design

Professor

Qiuting Huang

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