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High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT - Revision history
2024-03-28T22:20:09Z
Revision history for this page on the wiki
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Mocquard at 09:45, 20 August 2021
2021-08-20T09:45:04Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:45, 20 August 2021</td>
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<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>===Status: <del class="diffchange diffchange-inline">Available </del>===</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>===Status: <ins class="diffchange diffchange-inline">Completed </ins>===</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Looking for 1-2 Semester students</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Looking for 1-2 Semester students</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Lwu | Lianbo Wu]]</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Lwu | Lianbo Wu]]</div></td></tr>
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<td colspan="2" class="diff-lineno">Line 48:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div># R. B. Staszewski and P. T. Balsara, "All-Digital Frequency Synthesizer in Deep-Submicron CMOS", New Jersey: John Wiley & Sons, Inc., 261 pages, ISBN: 978-0471772552, Sept. 2006. DOI: 10.1002/9780470041956.  </div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div># R. B. Staszewski and P. T. Balsara, "All-Digital Frequency Synthesizer in Deep-Submicron CMOS", New Jersey: John Wiley & Sons, Inc., 261 pages, ISBN: 978-0471772552, Sept. 2006. DOI: 10.1002/9780470041956.  </div></td></tr>
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Mocquard
http://iis-projects.ee.ethz.ch/index.php?title=High_Performance_Digitally-Assisted_Time_Domain_ADC_Design_for_DPLL_used_in_Cellular_IOT&diff=4380&oldid=prev
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2018-12-04T16:07:20Z
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Brunn
http://iis-projects.ee.ethz.ch/index.php?title=High_Performance_Digitally-Assisted_Time_Domain_ADC_Design_for_DPLL_used_in_Cellular_IOT&diff=2448&oldid=prev
Lwu at 11:56, 20 September 2016
2016-09-20T11:56:42Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 11:56, 20 September 2016</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l46" >Line 46:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Links==  </div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Links==  </div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div># R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New Jersey: John Wiley & Sons, Inc., 261 pages, ISBN: 978-0471772552, Sept. 2006. DOI: 10.1002/9780470041956.  </div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div># R. B. Staszewski and P. T. Balsara, <ins class="diffchange diffchange-inline">"</ins>All-Digital Frequency Synthesizer in Deep-Submicron CMOS<ins class="diffchange diffchange-inline">"</ins>, New Jersey: John Wiley & Sons, Inc., 261 pages, ISBN: 978-0471772552, Sept. 2006. DOI: 10.1002/9780470041956.  </div></td></tr>
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Lwu
http://iis-projects.ee.ethz.ch/index.php?title=High_Performance_Digitally-Assisted_Time_Domain_ADC_Design_for_DPLL_used_in_Cellular_IOT&diff=2447&oldid=prev
Lwu at 11:56, 20 September 2016
2016-09-20T11:56:05Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 11:56, 20 September 2016</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l46" >Line 46:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Links==  </div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Links==  </div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"># R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New Jersey: John Wiley & Sons, Inc., 261 pages, ISBN: 978-0471772552, Sept. 2006. DOI: 10.1002/9780470041956. </ins></div></td></tr>
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Lwu
http://iis-projects.ee.ethz.ch/index.php?title=High_Performance_Digitally-Assisted_Time_Domain_ADC_Design_for_DPLL_used_in_Cellular_IOT&diff=2443&oldid=prev
Lwu at 11:53, 20 September 2016
2016-09-20T11:53:23Z
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Lwu
http://iis-projects.ee.ethz.ch/index.php?title=High_Performance_Digitally-Assisted_Time_Domain_ADC_Design_for_DPLL_used_in_Cellular_IOT&diff=2438&oldid=prev
Lwu at 11:29, 20 September 2016
2016-09-20T11:29:30Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 11:29, 20 September 2016</td>
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<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>[[File:Vernier-delay-line-based-TDC.png|thumb|<del class="diffchange diffchange-inline">600px</del>|Typical Vernier Delay Line based TDC (Time to Digital Convertor)]]</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>[[File:Vernier-delay-line-based-TDC.png|thumb|<ins class="diffchange diffchange-inline">400px</ins>|Typical Vernier Delay Line based TDC (Time to Digital Convertor)]]</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Short Description==</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Short Description==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">Tough frequency synthesize requirement imposed by cellular applications have been a key driver for PLL research in recent years. </del>As the <del class="diffchange diffchange-inline">age of cellular internet of things </del>is <del class="diffchange diffchange-inline">coming</del>, <del class="diffchange diffchange-inline">motivation for designing power efficient PLL (supreme phase noise performance at low power) </del>is <del class="diffchange diffchange-inline">getting stronger </del>than <del class="diffchange diffchange-inline">ever</del>. <del class="diffchange diffchange-inline">Locating at </del>the <del class="diffchange diffchange-inline">heart </del>of PLL<del class="diffchange diffchange-inline">, VCO does not only determine </del>the <del class="diffchange diffchange-inline">phase noise performance </del>of <del class="diffchange diffchange-inline">PLL </del>(<del class="diffchange diffchange-inline">especially far out part</del>) <del class="diffchange diffchange-inline">but also contributes considerably </del>to the <del class="diffchange diffchange-inline">total power budget</del>. <del class="diffchange diffchange-inline">As </del>the <del class="diffchange diffchange-inline">result</del>, <del class="diffchange diffchange-inline">stringent design specifications provide considerable incentive for research solely focused on improving the voltage</del>-<del class="diffchange diffchange-inline">controlled oscillator (VCO) performance</del>, <del class="diffchange diffchange-inline">one of </del>the <del class="diffchange diffchange-inline">most challenging aspects of PLL design. The </del>aim of this project is to analyze and build <del class="diffchange diffchange-inline">such </del>a <del class="diffchange diffchange-inline">power efficient sub-10 mW Digital controlled Oscillator (DCO) for GHz frequency range, to achieve a state</del>-of<del class="diffchange diffchange-inline">-art performance, finally leading </del>the <del class="diffchange diffchange-inline">way to a low </del>power <del class="diffchange diffchange-inline">low jitter Digital PLL</del>.  </div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>As <ins class="diffchange diffchange-inline">CMOS process node is progressing towards quantum level, voltage headroom is reduced correspondingly while transistor speed is increased on </ins>the <ins class="diffchange diffchange-inline">other hand. Therefore, it </ins>is <ins class="diffchange diffchange-inline">time to use time</ins>, <ins class="diffchange diffchange-inline">indicating that it </ins>is <ins class="diffchange diffchange-inline">beneficial to incorporate signal information into time domain rather </ins>than <ins class="diffchange diffchange-inline">conventional analog voltage domain</ins>. <ins class="diffchange diffchange-inline">This gives </ins>the <ins class="diffchange diffchange-inline">birth </ins>of <ins class="diffchange diffchange-inline">phase domain Digital </ins>PLL <ins class="diffchange diffchange-inline">and thus </ins>the <ins class="diffchange diffchange-inline">emerging </ins>of <ins class="diffchange diffchange-inline">time domain ADC. Compared with its mature analog counterpart topic </ins>(<ins class="diffchange diffchange-inline">Phase/Frequency Detector+ Charge Pump</ins>)<ins class="diffchange diffchange-inline">, concept of ADC is leveraged into DPLL </ins>to <ins class="diffchange diffchange-inline">quantize analog phase /frequency error in time domain. This topic is drawing more and more attention over </ins>the <ins class="diffchange diffchange-inline">past 5 years as seen in numerous top publications and patents</ins>. <ins class="diffchange diffchange-inline">Highly digitally-assisted analog design is </ins>the <ins class="diffchange diffchange-inline">trend for time domain ADC, such as DTC+TDC</ins>, <ins class="diffchange diffchange-inline">Bang</ins>-<ins class="diffchange diffchange-inline">Bang Detector. Following such a trend</ins>, the aim of this project is to analyze and build a <ins class="diffchange diffchange-inline">time domain ADC innovatively so that the in</ins>-<ins class="diffchange diffchange-inline">band jitter contribution </ins>of the <ins class="diffchange diffchange-inline">DPLL could be lower than 500fs while consuming </ins>power <ins class="diffchange diffchange-inline">less than 1 mW</ins>.  </div></td></tr>
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Lwu
http://iis-projects.ee.ethz.ch/index.php?title=High_Performance_Digitally-Assisted_Time_Domain_ADC_Design_for_DPLL_used_in_Cellular_IOT&diff=2437&oldid=prev
Lwu: Created page with "Typical Vernier Delay Line based TDC (Time to Digital Convertor) ==Short Description== Tough frequency synthesize require..."
2016-09-20T11:28:51Z
<p>Created page with "<a href="/index.php?title=File:Vernier-delay-line-based-TDC.png" title="File:Vernier-delay-line-based-TDC.png">thumb|600px|Typical Vernier Delay Line based TDC (Time to Digital Convertor)</a> ==Short Description== Tough frequency synthesize require..."</p>
<p><b>New page</b></p><div>[[File:Vernier-delay-line-based-TDC.png|thumb|600px|Typical Vernier Delay Line based TDC (Time to Digital Convertor)]]<br />
==Short Description==<br />
Tough frequency synthesize requirement imposed by cellular applications have been a key driver for PLL research in recent years. As the age of cellular internet of things is coming, motivation for designing power efficient PLL (supreme phase noise performance at low power) is getting stronger than ever. Locating at the heart of PLL, VCO does not only determine the phase noise performance of PLL (especially far out part) but also contributes considerably to the total power budget. As the result, stringent design specifications provide considerable incentive for research solely focused on improving the voltage-controlled oscillator (VCO) performance, one of the most challenging aspects of PLL design. The aim of this project is to analyze and build such a power efficient sub-10 mW Digital controlled Oscillator (DCO) for GHz frequency range, to achieve a state-of-art performance, finally leading the way to a low power low jitter Digital PLL. <br />
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===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Lwu | Lianbo Wu]]<br />
===Prerequisites===<br />
: AIC<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
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: Supervision: [[:User:Belfanti | Sandro Belfanti]]<br />
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===Character===<br />
: 30% Theory<br />
: 70% Circuit Design<br />
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===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
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[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Hot]]<br />
[[Category:Semester Thesis]]<br />
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[[#top|↑ top]]<br />
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Lwu