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Difference between revisions of "Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator"

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[[Category:Semester Thesis]]
[[Category:Semester Thesis]]

Revision as of 10:12, 11 February 2015

Leveling Loop for Very-Low-Distortion Oscillator.jpg

Short Description

A key quality parameter of audio signal paths is their distortion performance. For distortion measurements, an oscillator with very low harmonic content (i.e. itself has very low distortion) and noise is necessary. For state-of-the-art resolution, fully analog RC oscillators are required. To stabilize their amplitude, a leveling loop consisting of level detector, error integrator and a multiplier is employed. Implementation of this leveling loop is critical to oscillator performance (e.g. it affects harmonic distortion, settling time and sideband noise) and poses several demanding tradeoffs. This semester thesis investigates a hybride implementation, where the signal path of the leveling loop comprises an AD converter and a multiplying DA converter, with intermediate digital signal processing (FPGA or DSP). Carried out with an industry partner (Weiss Engineering Ltd.).

Status: Available

Looking for 1-2 Semester students
Contact: Norbert Felber


Interest in high-performance mixed signal circuit design;
Background in hardware design and low-level sofware implementation (e.g. VHDL or assembler) beneficial


70% Hardware Implementation
30% Software Implementation


Hubert Kaeslin

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Detailed Task Description


Practical Details



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