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Hypervisor Extension for Ariane (M)

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Ariane is an open-source, 6-stage, 64-bit, in-order RISC-V core developed at IIS [1]. It is capable of booting Linux and it is widely used both in academia and industry. To support common operating systems, Ariane features three privilege levels (Machine-, Supervisor-, and User-Mode) and address translation as described in the RISC-V privileged ISA [2].

The RISC-V Hypervisor Extension ([2], pages 79-112) adds Hypervisor mode to the three existing privilege levels. This mode supports the virtualization and isolation of guest operating systems (OSes) – a common technique used in secure systems and cloud computing to allow running untrusted OSes or multiple OSes in parallel.


The goal of this project is to implement the Hypervisor extension as an optional feature in Ariane. The reqiured modifications include

  • adding a second stage of address translation,
  • extending the CSR (control and status register) register file by hypervisor-mode versions of existing CSRs and newly defined CSRs required for the second stage address translation, and
  • adding newly defined instructions for loads and stores from hypervisor mode to virtual memory, and for flushing the TLBs (hfence).

The implemented features shall be verified and their hardware costs evaluated. The experiences gained during this work can be fed back to the RISC-V community and contribute to the development of the Hypervisor specification.

Depending on the work’s progress, the Hypervisor extension's functionality can be demonstrated by porting a hypervisor to Ariane and running multiple OSes on top.

  • Strong interest in computer architecture
  • Experience with HDLs (preferably SystemVerilog) such as taught in VLSI I
  • Knowledge of ASIC tool flow (Synthesis) or parallel enrollment with VLSI II is of benefit.

Composition: 20% Architecture specification, 50% Verification, 30% RTL Implementation

Status: In Progress