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Ibex: Tightly-Coupled Accelerators and ISA Extensions

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Ibex is a 32-bit in-order RISC-V core implementing the RV32IC instruction set. Its design is of high-quality, open source and it comes with an industry-grade verification environment. In addition, there are several configuration options such as optional support for the RISC-V E, M, and B instruction set architecture (ISA) extensions, different multiplier options, a separate branch-target ALU, write-back stage and static branch predictor. Thanks to these options, Ibex can cover a variety of application scenarios ranging from small and efficient, 2-stage pipeline designs to beefier, 3-stage pipeline configurations for higher performance (3.13 CoreMark/MHz) or with additional security features.

Recently, support for a new extension interface has been added. This interface provides a generalized framework suitable to implement custom co-processors and ISA extensions for existing RISC-V processor cores. Just like Ibex [1], the work for this extension interface has been started at ETH Zürich and University of Bologna. In the meantime, a working group has been formed connecting academia with industry partners. This group involves both the not-for-profit company lowRISC C.I.C. maintaining Ibex as well as members of the OpenHW Group that continue to drive the extension interface forward.

Short Description

The goal of this project is to implement a tightly-coupled co-processor/accelerator or ISA extension for Ibex using the new extension interface and thereby providing useful input to the working group and contributing to the further development of the extension interface. As for the actual co-processor/accelerator or ISA extension to implement, there are plenty of options such as interfacing an existing accelerators like floating-point units (FPU) or a vector processing unit (VPU), or the development of a new accelerator such as a string co-processor. The project can be done in the context of a single-core or multi-core system such as PULP where the accelerator is shared by multiple Ibex cores.

This project is a joint collaboration between IIS, lowRISC and OpenHW Group. You will actively participate in working group meetings, share your results and get valuable feedback. As such, you can contribute to the further development and potential standardization of the extension interface. You don't have to be an expert in the field of computer architecture and accelerators to successfully master this project. The project builds on top of existing, high-quality, open-source IP and verification infrastructure and you will be accompanied by experts in the various fields. What we need you to bring into the project is basic knowledge in integrated circuit design (VLIS I/II lectures), team working skills, self-motivation, drive and a positive attitude toward challenge.

Your main tasks will be:

  • Together with your supervisors and based on your experience/skill set/team/project duration, select an existing co-processor accelerator to interface or a new one to develop from scratch.
  • Familiarize with the Ibex design and the extension interface.
  • Do a design-space exploration for interfacing your accelerator. This includes ASIC/FPGA synthesis, analysis of area cost and timing.
  • Participate and contribute to meetings of the extension interface working group.
  • Verification of the accelerator and interface using riscv-dv.

Status: Available

Looking for 1-2 Interested Master Students (Semester Project)
Supervision: Pirmin Vogel, Samuel Riedel, Matheus Cavalcante, Pasquale Davide Schiavone


20% Theory, computer architecture
60% Design space exploration: RTL design, simulation, benchmarking
20% Verification


Basics in VLSI design (VLSI1 course), SystemVerilog, computer architecture
Experience with using the GNU Compiler Collection (GCC) or LLVM+Clang is beneficial
Motivation to work hard on a cool open-source project


Luca Benini


  1. P.D. Schiavone, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications", Proceedings of the 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, Greece, 2017. link

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