Inexact sub-near-threshold systems for ultra-low power devices
The notion of exact computation, where outputs of the computational element (circuit) have precise deterministic values, as well as the fact that electronic chips are powered at nominal voltages for increased performances, have been pervasive in the computing domain for many decades owing to the overwhelming success of the integrated circuit design using reliable transistors, particularly in Complementary Metal-Oxide-Semiconductor (CMOS) technology. However, semiconductor industry is facing serious challenges today as diminishing transistor sizes driven by Moore’s law are leading to increasing process variations and additional perturbations due to temperature and voltage fluctuations which threaten the circuit functionality.
Owing to such widely anticipated hurdles to continued technology scaling - the promise of Moore’s law - and a growing desire for reducing energy consumption, techniques and technologies such as inexact/approximate circuits and sub- or near-threshold circuits (supply voltage below or near the transistor threshold voltages) have gained prominence. The first radical approach realizes parsimonious or “adequately engineered” designs that trade accuracy at the hardware level for significant gains in energy consumption, area, and speed. The second approach offers the minimal power or energy consumption at the cost of increased delay and power variations. A large class of energy constrained systems, particularly in the domain of embedded portable multimedia and in domains of budding interest such as recognition, search and data mining, lend themselves readily for such a design philosophy. In fact, all of which can tolerate inaccuracies to varying extents or can synthesize accurate (or sufficient) information even from inaccurate computations.
Until now, these research works have been limited to application-specific instances of building blocks that were mostly ad-hoc targeting some specific examples and did not consider well-understood complete platforms based on these inexact and extreme low voltage components in sub- or near-threshold operation. In addition, research was conducted without a synergy between inexact computing and extreme low voltage circuits. It is therefore mandatory to consider at the same time the design of various inexact, approximate, sub- or near-threshold components and the platform consisting of these components. The platform design will be largely impacted by the usage of these components, in terms of parallelism, performances and robustness. One has to revisit the system design in terms of usage of hardware accelerators, heterogeneous or homogeneous processor cores and of communication or network-on-chip that has to be implemented for data transmission.
It has been demonstrated that inexact arithmetic blocks could provide a reduction up to 15X in delay, power and area product. Sub- or near-threshold circuits could provide a reduction of 6X in dynamic power when reducing the supply voltage from 1.0 V. to 0.4V. The platform design, while using very energy-efficient hardware accelerators, will contribute to the significant power reduction expected from the combination of the aforementioned techniques.
We will address practical issues by using the proposed techniques to fabricate prototype chips implementing large-scale error resilient systems and through physical measurements to validate and demonstrate evidence of the utility of these techniques both quantitatively (through well-defined application-specific quality metrics) and qualitatively, yielding perceptually discernible outputs (such as audio, image or video data).