Latest revision as of 14:22, 27 February 2024

Overview

Status: In Progress

• Type: Semester Thesis or Master Thesis
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Michael Rogenmoser: michaero@iis.ee.ethz.ch

Introduction

In the PULP group, we have started developing reliable hardware designed for use in space, where high levels of radiation have a significant impact on the correctness of executions.

Memories and Caches are some of the most vulnerable components in a SoC [1]. Thus, we would like to implement efficient protection mechanisms for the caches we use throughout our SoCs.

Project

In this project, you will expand the last-level cache [2] developed in the PULP group with fault tolerance mechanisms. These include parity bits, Error Correcting Codes (ECC), and possibly other mechanisms. The aim is to ensure that faults affecting the stored date, but also the control information, are properly detected and corrected. The goal is to implement multiple approaches and properly evaluate their performance and efficiency, as well as their fault tolerance. To properly evaluate the approach, some literature research is needed and the implementation will need to be compared to related work, such as [2].

Character

• 10% Literature Research
• 50% Architecture Design and Exploration
• 20% Performance and Fault Tolerance Evaluation
• 20% Documentation & Report

Prerequisites

• Experience with digital design in SystemVerilog as taught in VLSI I
• Knowledge about how caches work is beneficial

References

• [1] https://ieeexplore.ieee.org/document/8875424/
• [2] https://github.com/pulp-platform/axi_llc
• [3] https://doi.org/10.1145/1555754.1555771