Implementation of a Coherent Application-Class Multicore System (1-2S)
From iis-projects
Contents
Status: Available
Introduction
Ariane is an open-source, 6-stage, 64-bit, in-order RISC-V core developed at IIS [1]. It is capable of booting Linux and it is widely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally stores a copy of recently accessed memory contents to accelerate future accesses to this data.
To increase a system's performance on parallel workloads, a common technique is to combine multiple instances of a core to a multi-core system. This technique introduces a new challenge: Each core keeps its own copy of the (partial) main memory in its respective L1 data cache. Working of different copies of the same data can quickly result in inconsistencies between the cores' memory views.
This challenge can be tackled by introducing cache-coherence, a set of mechanisms that keep the local caches synchronized and up-to-date. Cache coherence for Ariane is currently under development and a prototype is expected to become available soon.
Project
The goal of this project is to implement a chip featuring multiple coherent Ariane cores. Throughout this project, the feasibility and performance of the system shall be evaluated.
Requirements
- Strong interest in computer architecture
- Experience with HDLs (preferably SystemVerliog) such as taught in VLSI I
- Knowledge of ASIC tool flow (Synthesis) or parallel enrollment with VLSI II
Composition: 20% RTL Implementation, 50% Chip Backend, 30% Verification
