Information for "Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core"
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Basic information
| Display title | Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core |
| Default sort key | Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core |
| Page length (in bytes) | 3,856 |
| Page ID | 1116 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | Pschiavo (talk | contribs) |
| Date of page creation | 09:59, 14 June 2019 |
| Latest editor | Kgf (talk | contribs) |
| Date of latest edit | 08:42, 20 January 2021 |
| Total number of edits | 4 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
