View source for Implementing Configurable Dual-Core Redundancy

<!-- Implementing Configurable Dual-Core Redundancy (1M/S) -->

[[Category:Digital]]
[[Category:Fault Tolerance]]
[[Category:HW/SW Safety and Security]]
[[Category:Computer Architecture]]
[[Category:2022]]
[[Category:Semester Thesis]]
[[Category:Master Thesis]]
[[Category:Mbertuletti]]
[[Category:Michaero]]
[[Category:Completed]]


= Overview =

== Status: Completed ==

* Type: Master / Semester Thesis
* Professor: Prof. Dr. L. Benini
* Supervisors:
** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]
** [[:User:Sriedel | Samuel Riedel]]: [mailto:sriedel@iis.ee.ethz.ch sriedel@iis.ee.ethz.ch]
** [[:User:Mbertuletti | Marco Bertuletti]]: [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch]

= Introduction =

All computing systems, are vulnerable to runtime faults (Single Event Upsets, SEUs), especially when deployed in environments with high levels of radiation, such as space. To combat this, IIS has developed a Triple Modular Redundancy (TMR) approach at the core level, making use of the PULP cluster, with additional features to enable and disable the redundancy at runtime (On-Demand Redundancy Grouping, ODRG)[[#ref-Rogenmoser2022|&#91;1&#93;]]. 

At ETH, we are developing our own many-core system called MemPool [[#ref-Cavalcante2020|&#91;2&#93;]], [[#ref-Riedel2021|&#91;3&#93;]]. It boasts 256 lightweight 32-bit Snitch cores [[#ref-Zaruba2020|&#91;4&#93;]]. They implement the RISC-V instruction set architecture (ISA), a modular and open ISA [[#ref-Waterman2019|&#91;5&#93;]]. Despite its size, MemPool manages to give all 256 cores low-latency access to the shared L1 memory, with a zero-load latency of at most five cycles. Therefore, all cores can efficiently communicate, making MemPool suitable for various workloads and easy to program.

= Project =

While TMR works very well for fast recovery, using three cores for fault tolerance has a 200% overhead in area and power consumption, which for certain use-cases is not tenable. The goal of this project would be to implement configurable Dual Modular Redundancy at the core-level within a MemPool cluster, allowing a single tile to switch between a 4-core or a reliable 2-core mode. A two-core redundancy mechanism has some more challenges compared to a three-core approach, as the correct state is not known, requiring more involved recovery schemes. 

== Character ==

* 20% Hardware and Software familiarization
* 50% Hardware Design
* 30% Reliability Evaluation

== Prerequisites ==

* Experience with digital design in SystemVerilog as taught in VLSI I
* Strong interest in Computer Architecture and Reliable Computing

= References =
<div id="refs" class="references">
<div id="ref-Rogenmoser2022">
&#91;1&#93; M. Rogenmoser, N. Wistoff, P. Vogel, F. Gürkaynak, L. Benini, “On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster,” in ''2022 IEEE Computer Society Annual Symposium on VLSI'' 2022.
</div>
<div id="ref-Cavalcante2020">
&#91;2&#93; M. Cavalcante, S. Riedel, A. Pullini, and L. Benini, “MemPool: A shared-L1 memory many-core cluster with a low-latency interconnect,” in ''2021 design, automation, and test in europe conference and exhibition (date)'', 2021, pp. 701–706.
</div>
<div id="ref-Riedel2021">
&#91;3&#93; S. Riedel and M. Cavalcante, “MemPool GitHub.” 2021.
</div>
<div id="ref-Zaruba2020">
&#91;4&#93; F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads,” ''IEEE TRANSACTIONS ON COMPUTERS'', pp. 1–1, Feb. 2020.
</div>
<div id="ref-Waterman2019">
&#91;5&#93; A. Waterman and K. Asanović, “The RISC-V Instruction Set Manual Volume I: Unprivileged ISA - Document Version 20191213,” RISC-V Foundation, 2019.
</div>
</div>