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Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)

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Status: Available


Recently, a wide range of free and open-source electronic design automation (EDA) tools are emerging. Whilst being highly diverse in terms of application, they all share a common weakness; these tools only feature very limited SystemVerilog (SV) support.

Our digital designs at IIS are written using the entire subset of synthesizable SystemVerilog code rendering most of our projects (PULP, Snitch, Ariane, ...) incompatible with most EDA tools.

One solution to fix this issue would be a step-by-step simplification of the constructs that are not supported by the target EDA tool.

The slang project is a lightweight SystemVerilog parser written in C++ with the best SV support within the open-source domain see SV-Test Leaderboard. Slang can parse SV, preprocess macros and includes, propagate constant parameters, uniquify the instances, and perform basic elaboration on the sourcecode. As a result, it produces an abstract syntax tree (AST) representation of the SV code as a JSON file. The simplification passes can then be done on the AST facilitating both their implementation and the check for correctness of the pass. Once transformed, slang can read the AST and reemit simpler SV code.


In this project, you will try to synthesize a Linux-capable SoC built around Ariane (CVA6) using Yosys. To allow Yosys to read the sourcecode of Ariane, you will use slang to stepwise simplify the SV code as outlined above.


  • 20% analysis of slang
  • 30% analysis of the SV support of Yosys and the Ariane sourcecode: Which constructs cannot be understood by Yosys
  • 50% implement and verify the simplification passes of the SV code


  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Knowledge of C++ and Python
  • Preferred: Experience with frontend compiler design and/or ASTs
  • Preferred: Experience with FOSS EDA tools