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[[Category:2023]]
 
[[Category:2023]]
 
[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
[[Category:Available]]
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[[Category:Completed]]
 
[[Category:Lbertaccini]]
 
[[Category:Lbertaccini]]
  
 
= Overview =
 
= Overview =
  
== Status: Available ==
+
== Status: Completed ==
  
 
* Type: Semester Thesis (1 or 2 students)
 
* Type: Semester Thesis (1 or 2 students)
 +
* Student: Roman Marquart
 
* Professor: Prof. Dr. L. Benini
 
* Professor: Prof. Dr. L. Benini
 
* Supervisors:
 
* Supervisors:
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= Introduction =
 
= Introduction =
[[File:FPU_with_DivSqrt.png|thumb|300px|CVFOU block diagram [1]. CVFPU is a modular floating-point unit (FPU) in which each operation group block can be instantiated through a parameter. ]]
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[[File:FPU_with_DivSqrt.png|thumb|300px|CVFPU block diagram [1]. CVFPU is a modular floating-point unit (FPU) in which each operation group block can be instantiated through a parameter. ]]
  
 
Floating-point (FP) arithmetic is fundamental for a large set of applications spanning from high-performance computing to neural network training. A flexible highly-parametrized open-source floating-point unit (FPU) called FPnew (today known as CVFPU) [1,2] has been developed at IIS.  
 
Floating-point (FP) arithmetic is fundamental for a large set of applications spanning from high-performance computing to neural network training. A flexible highly-parametrized open-source floating-point unit (FPU) called FPnew (today known as CVFPU) [1,2] has been developed at IIS.  
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FPnew is optimized for high-performance and energy efficiency. It is internally organized in modules, each one carrying out one operation group (add/mul, divsqrt, cast, comparisons, dot-product).
 
FPnew is optimized for high-performance and energy efficiency. It is internally organized in modules, each one carrying out one operation group (add/mul, divsqrt, cast, comparisons, dot-product).
  
Recently, T-Head open sourced a set of processors. The goal of this project is to evaluate the double-precision DivSqrt unit included in the open-source T-head OpenC906 processor and integrate it into CVFPU.
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Recently, T-Head open sourced a set of processors. The goal of this project is to evaluate the double-precision DivSqrt unit included in the open-source T-head OpenC910 [3] processor and integrate it into CVFPU.
  
  
 
= Project =
 
= Project =
  
* '''Investigation of the T-Head OpenC906 FP DivSqrt module and its fundamental blocks'''
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* '''Investigation of the T-Head OpenC910 FP DivSqrt module and its fundamental blocks'''
  
* '''RTL integration of T-Head OpenC906 FP DivSqrt module into CVFPU'''
+
* '''RTL integration of T-Head OpenC910 FP DivSqrt module into CVFPU'''
  
 
* '''Evaluation of the FP DivSqrt module and the enhanced CVFPU'''
 
* '''Evaluation of the FP DivSqrt module and the enhanced CVFPU'''
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[2] https://github.com/openhwgroup/cvfpu
 
[2] https://github.com/openhwgroup/cvfpu
  
[3] https://github.com/T-head-Semi/openc906
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[3] https://github.com/T-head-Semi/openc910
  
  
===Status: Available ===
+
===Status: Completed ===

Latest revision as of 14:40, 15 February 2024


Overview

Status: Completed

Introduction

CVFPU block diagram [1]. CVFPU is a modular floating-point unit (FPU) in which each operation group block can be instantiated through a parameter.

Floating-point (FP) arithmetic is fundamental for a large set of applications spanning from high-performance computing to neural network training. A flexible highly-parametrized open-source floating-point unit (FPU) called FPnew (today known as CVFPU) [1,2] has been developed at IIS.

FPnew is optimized for high-performance and energy efficiency. It is internally organized in modules, each one carrying out one operation group (add/mul, divsqrt, cast, comparisons, dot-product).

Recently, T-Head open sourced a set of processors. The goal of this project is to evaluate the double-precision DivSqrt unit included in the open-source T-head OpenC910 [3] processor and integrate it into CVFPU.


Project

  • Investigation of the T-Head OpenC910 FP DivSqrt module and its fundamental blocks
  • RTL integration of T-Head OpenC910 FP DivSqrt module into CVFPU
  • Evaluation of the FP DivSqrt module and the enhanced CVFPU

Project Breakdown

  • 20% Architecture review
  • 40% RTL implementation
  • 40% Evaluation

Prerequisites

  • Strong interest in computer architecture
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Experience with ASIC implementation flow (synthesis) as taught in VLSI II

References

[1] Mach, S., Schuiki, F., Zaruba, F., & Benini, L. (2020). FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(4), 774-787. (https://ieeexplore.ieee.org/abstract/document/9311229)

[2] https://github.com/openhwgroup/cvfpu

[3] https://github.com/T-head-Semi/openc910


Status: Completed