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Difference between revisions of "PULP’s CLIC extensions for fast interrupt handling"

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<!-- Integration and Implementation of Alibaba’s T-Head CLIC Interrupt Controller in PULP SoC -->
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<!-- Integration of Alibaba’s T-Head Opene906 processor in PULP Power Controller Subsystem -->
  
 
[[Category:Digital]]
 
[[Category:Digital]]
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Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor.
 
Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor.
 
T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1].
 
T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1].
Xuantie E902 and E906 processors implement the Core-Local Interrupt Controller (CLIC) [2], a newly proposed RISC-V interrupt controller promising low-latency, vectored, pre-emptive interrupts to meet the needs of Real-Time embedded systems.
 
  
 
= Project =
 
= Project =
  
At IIS we recently developed an in-house CLIC IP, which is coupled with the CV32E40P processor [4] within the PULPissimo SoC platform.
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PULPissimo is an open-source, single core RISC-V microcontroller [5] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [4].  
PULPissimo is a RISC-V microcontroller [5] developed by PULP.  
 
  
The goal of this project is to:
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The goal of this project is to replace our in-house processor with T-Head’s Opene906:
* Study the RISC-V CLIC specifications and T-Head’s CLIC source code. We at IIS we have forked T-Head's processors sourcecode to support our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead.
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* Study T-Head’s opene906 source code.  
* Integrate T-Head’s CLIC into PULPissimo and couple it with CV32E40P
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* For the latter, at IIS we have forked T-Head’s processors in our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead.
* Verify functional correctness in simulation and measure interrupt latency
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* Integrate T-Head’s opene906 into PULPissimo to replace the existing processor developed by PULP, CV32E40P
* Synthesize and compare with PULP’s CLIC (area/timing reports)
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* Verify basic functional correctness in simulation
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* Synthesize the new processor, evaluate area and timing figures
 
* ASIC Backend flow towards PULPissimo SoC tapeout
 
* ASIC Backend flow towards PULPissimo SoC tapeout
  
 
== Character ==
 
== Character ==
  
* 10% Literature / architecture review
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* 15% Literature / architecture review
* 40% RTL implementation
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* 30% RTL implementation
 
* 30% Backend
 
* 30% Backend
* 20% Evaluation
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* 25% Evaluation
  
 
== Prerequisites ==
 
== Prerequisites ==
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[1] https://github.com/T-head-Semi (GitHub repository)
 
[1] https://github.com/T-head-Semi (GitHub repository)
 
[2] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc (GitHub repository)
 
  
 
[3] https://github.com/bluewww/opene906 (GitHub repository)
 
[3] https://github.com/bluewww/opene906 (GitHub repository)

Revision as of 19:04, 20 January 2022


Overview

Status: Available

Introduction

Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor. T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1].

Project

PULPissimo is an open-source, single core RISC-V microcontroller [5] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [4].

The goal of this project is to replace our in-house processor with T-Head’s Opene906:

  • Study T-Head’s opene906 source code.
  • For the latter, at IIS we have forked T-Head’s processors in our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead.
  • Integrate T-Head’s opene906 into PULPissimo to replace the existing processor developed by PULP, CV32E40P
  • Verify basic functional correctness in simulation
  • Synthesize the new processor, evaluate area and timing figures
  • ASIC Backend flow towards PULPissimo SoC tapeout

Character

  • 15% Literature / architecture review
  • 30% RTL implementation
  • 30% Backend
  • 25% Evaluation

Prerequisites

  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Must have visited VLSI II in a previous semester or take it alongside the thesis

References

[1] https://github.com/T-head-Semi (GitHub repository)

[3] https://github.com/bluewww/opene906 (GitHub repository)

[4] https://github.com/openhwgroup/cv32e40p (GitHub repository)

[5] https://github.com/pulp-platform/pulpissimo (GitHub repository)