Difference between revisions of "PULP’s CLIC extensions for fast interrupt handling"
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− | <!-- Integration | + | <!-- Integration of Alibaba’s T-Head Opene906 processor in PULP Power Controller Subsystem --> |
[[Category:Digital]] | [[Category:Digital]] | ||
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Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor. | Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor. | ||
T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1]. | T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1]. | ||
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= Project = | = Project = | ||
− | + | PULPissimo is an open-source, single core RISC-V microcontroller [5] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [4]. | |
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− | The goal of this project is to: | + | The goal of this project is to replace our in-house processor with T-Head’s Opene906: |
− | * Study | + | * Study T-Head’s opene906 source code. |
− | * Integrate T-Head’s | + | * For the latter, at IIS we have forked T-Head’s processors in our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead. |
− | * Verify functional correctness in simulation | + | * Integrate T-Head’s opene906 into PULPissimo to replace the existing processor developed by PULP, CV32E40P |
− | * Synthesize and | + | * Verify basic functional correctness in simulation |
+ | * Synthesize the new processor, evaluate area and timing figures | ||
* ASIC Backend flow towards PULPissimo SoC tapeout | * ASIC Backend flow towards PULPissimo SoC tapeout | ||
== Character == | == Character == | ||
− | * | + | * 15% Literature / architecture review |
− | * | + | * 30% RTL implementation |
* 30% Backend | * 30% Backend | ||
− | * | + | * 25% Evaluation |
== Prerequisites == | == Prerequisites == | ||
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[1] https://github.com/T-head-Semi (GitHub repository) | [1] https://github.com/T-head-Semi (GitHub repository) | ||
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[3] https://github.com/bluewww/opene906 (GitHub repository) | [3] https://github.com/bluewww/opene906 (GitHub repository) |
Revision as of 19:04, 20 January 2022
Contents
Overview
Status: Available
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor. T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1].
Project
PULPissimo is an open-source, single core RISC-V microcontroller [5] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [4].
The goal of this project is to replace our in-house processor with T-Head’s Opene906:
- Study T-Head’s opene906 source code.
- For the latter, at IIS we have forked T-Head’s processors in our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead.
- Integrate T-Head’s opene906 into PULPissimo to replace the existing processor developed by PULP, CV32E40P
- Verify basic functional correctness in simulation
- Synthesize the new processor, evaluate area and timing figures
- ASIC Backend flow towards PULPissimo SoC tapeout
Character
- 15% Literature / architecture review
- 30% RTL implementation
- 30% Backend
- 25% Evaluation
Prerequisites
- Experience with digital design in SystemVerilog as taught in VLSI I
- Must have visited VLSI II in a previous semester or take it alongside the thesis
References
[1] https://github.com/T-head-Semi (GitHub repository)
[3] https://github.com/bluewww/opene906 (GitHub repository)
[4] https://github.com/openhwgroup/cv32e40p (GitHub repository)
[5] https://github.com/pulp-platform/pulpissimo (GitHub repository)