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Level Crossing ADC For a Many Channels Neural Recording Interface

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Introduction

LC-ADC.png

Project description

The student is required to:

Required Skills

To work on this project, you will need:

  • to have prior knowedge of analog circuit design

Other skills that you might find useful include:

  • familiarity with a scripting language
  • to be strongly motivated for a super-cool project

Status: Available

Supervision: Alfio Di Mauro

Professor

Taekwang Jang, Luca Benini

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Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.


Literature

  • [Rovere2017] A 2.2 µW Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes [2]
  • [Liu2018] Event-driven processing for hardware-efficient neural spike sorting [3]

Links

  • The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [4]
  • The IIS/DZ coding guidelines [5]


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