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Level Crossing ADC For a Many Channels Neural Recording Interface

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Over the last five decades, the number of simultaneously recorded neurons has doubled approximately every 7 year [Stevenson2011]. This trend motivates researchers to find new approaches to analyse and process the increasing amount of collected data, which grows linearly with the number of recording channels. In this context, Level-Crossing Analog to Digital Converters (LC-ADC) could reduce the amount of information to transfer in case of low activity of the input signal, compared to more common Uniform-Sampling ADCs (UC-ADCs). Additionally, the asynchronous nature of this type of ADC output interface, enables very promising preliminary signal pre-processing [Liu2018], enabling a very effective information extraction already at the sensor edge.

Project description

In this project, it is proposed to the student the implementation of a low-power LC-ADC featuring a delta-modulated output transmission interface (asynchronous request and data signal).


The student is required to:

  • Propose modifications and improvements to an already existing implementation [Rovere2017] to address low power consumption and small area
  • Implement the ADC on umcL65 technology
  • Verify the implementation

Required Skills

To work on this project, you will need:

  • to have prior knowedge of analog circuit design

Other skills that you might find useful include:

  • familiarity with a scripting language
  • to be strongly motivated for a super-cool project

Status: Available

Supervision: Alfio Di Mauro


Taekwang Jang, Luca Benini

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Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.


  • [Stevenson2011] How advances in neural recording affect data analysis [2]
  • [Rovere2017] A 2.2 µW Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes [3]
  • [Liu2018] Event-driven processing for hardware-efficient neural spike sorting [4]


  • The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [5]
  • The IIS/DZ coding guidelines [6]↑ top