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| | ==Short Description== | | ==Short Description== |
| − | Imaging sensor networks, UAVs, smartphones, and other embedded computer vision systems require power-efficient, low-cost and high-speed implementations of synthetic vision systems capable of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almost all state-of-the-art synthetic vision systems are based on features extracted using multi-layer convolutional networks (ConvNets). When evaluating ConvNets, most of the time is spent performing the convolutions (80% to 90%). The focus of this work is on speeding up this step by creating an accelerator to perform this step faster and more power-efficiently.
| + | The master thesis will be carry on in collaboration with [http://www.abb.ch/cawp/abbzh254/ec72bb280fd24d47c1256b5700522f3a.aspx ABB CHCRC] and will focus on the implementation of an Active-Set quadratic program (QP) solver accelerator on FPGA. |
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| − | <!--
| + | QP problems arise in various embedded optimization applications such as model predictive control or constrained least-square fitting. Various solution algorithms have been proposed and implemented on CPUs (some of them also on FPGAs), each of them exhibiting specific advantages and drawbacks. Active-set methods are frequently used on CPUs for solving QPs efficiently, but their use on FPGAs is considered challenging as they rely on more involved linear algebra operations such as matrix factorizations. Aim of this thesis project is to investigate the potential of implementing an active-set method for FPGAs and to identify/adapt an existing scheme to be implemented in hardware. |
| − | More and more video surveillance data is being collect for real-time surveillance and storage. Privacy is a real issue, posing a legal obstacle when public places are being monitored: real-time surveillance is not allowed in such cases, and stored data can (even for internal use) only be accessed with a court order.
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| − | With the use of privacy enhancement techniques, this is different. Currently, such systems are often based on simple motion detection, blurring everything that has moved recently. This can be an option if there is little activity and only very low detail is needed. However, when monitoring a crowded area the results are useless and important detail such as the person's movements is completely hidden.
| + | ===Status: Available === |
| − | | + | : Looking for Interested Students |
| − | This project is supposed to overcome this by using deep learning techniques to detect pedestrians/persons and using temporal/motion information to improve the delineation of moving objects. This way the pedestrians can be overpainted, blurred, or overlaid with motion-based information, protecting their privacy while enabling better information to security personnel.
| + | : Type: Master Thesis |
| − | --->
| + | : Supervisors: [[:User:Barandre|Andrea Bartolini]], [[:User:schaffner|Michael Schaffner]] |
| − | ===Status: In Progress === | |
| − | : David Gschwend, Christoph Mayer, Samuel Willi | |
| − | : Supervision: [[:User:Lukasc | Lukas Cavigelli]], [[:User:muheim| Beat Muheim]] | |
| − | : Date: Fall Semester 2014 (sem14h17, sem14h18, sem14h19)
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| | | | |
| | ===Prerequisites=== | | ===Prerequisites=== |
| − | : Knowledge of Matlab | + | : VLSI I, VLSI II, Control Systems |
| − | : Interest in video processing and VLSI design
| + | : Matlab, C++, VHDL or System Verilog |
| − | : VLSI 1 and enrolment in VLSI 2 is required
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| − | : At least one student has to test the chip as part of the VLSI 3 lecture, if the ASIC should be manufactured.
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| − | <!--
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| − | ===Status: Completed ===
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| − | : Fall Semester 2014 (sem13h2)
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| − | : Matthias Baer, Renzo Andri
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| − | --->
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| − | <!--
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| − | ===Status: In Progress ===
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| − | : Student A, StudentB
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| − | : Supervision: [[:User:Mluisier | Mathieu Luisier]]
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| − | --->
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| | | | |
| | ===Character=== | | ===Character=== |
| − | : 10% Theory / Literature Research | + | : 20% Theory |
| − | : 60% VLSI Architecture, Implementation & Verification | + | : 60% Implementation |
| − | : 30% VLSI back-end Design | + | : 20% Testing |
| | + | |
| | + | ===Partners=== |
| | + | : [http://www.abb.ch/cawp/abbzh254/ec72bb280fd24d47c1256b5700522f3a.aspx ABB Corporate Research Center (CHCRC)] |
| | | | |
| | ===Professor=== | | ===Professor=== |
| | : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] | | : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] |
| | + | <!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---> |
| | + | <!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---> |
| | + | <!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---> |
| | + | <!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---> |
| | + | <!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---> |
| | [[#top|↑ top]] | | [[#top|↑ top]] |
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| | ===Goals=== | | ===Goals=== |
| − | : Explore various architectures to perform the 2D convolutions used in convolutional networks, considering the constraints of an ASIC design, and performing fixed-point analyses for the most viable architecture(s)
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| − | : Get to know the ASIC design flow from specification through architecture exploration to implementation, functional verification, back-end design and silicon testing.
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| − | ===Step-by-Step Workflow===
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| − | # Do some first project planning. Create a time schedule and set some milestones based on what you have learned as part of the VLSI lectures.
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| − | # Get to understand the basic concepts of convolutional networks.
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| − | # Catch up on relevant previous work, in particular the papers we give to you.
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| − | # Become aware of the possibilities and limitations of the used technology; make some very rough estimates of area and timing. Also consider setting some target specifications for your chip.
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| − | # Come up with and evaluate/discuss several possible architectures (architecture exploration), implement the datapath/most resource relevant parts to get some first impression of the most promissing architecture(s). Also give some first thoughts to testability.
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| − | # Run detailed fixed-point analyses to determine the signal width in all parts of the data path.
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| − | # Create high quality, synthesizable VHDL code for your circuit. Please respect the lab's coding guidelines and continuously verify proper functionality of the individual parts of your design.
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| − | # Implement the necessary configuration interface, ...
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| − | # Perform thorough functional verification. This is very important.
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| − | # Take your final implementation through the backend design process.
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| − | # Write a project report. Include all major decisions taken during the design process and argue your choice. Include everything that deviates from the very standard case -- show off everything that took time to figure out and all your ideas that have influenced the project.
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| − | Be aware, that these steps cannot always be performed one after the other and often need some initial guesses followed by several iterations.
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| − |
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| − | ===Meetings & Presentations===
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| − | The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed.
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| − | Around the middle of the project there is a design review, where senior members of the institue review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided.
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| − | At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.
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| − |
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| − | ===Deliverables===
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| − | * description of the most promising architectures, and argumentation on the decision taken (as part of the report)
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| − | * synthesizable, verified VHDL code
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| − | * generated test vector files
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| − | * synthesis scripts & relevant software models developed for verification
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| − | * GDS II data & bonding diagram
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| − | * datasheet (part of report)
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| − | * project report
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| − |
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| − | ===Literature===
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| − | NeuFlow [http://www.neuflow.org/] in general and in particular
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| − |
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| − | * C. Farabet, B. Martini, B. Corda, P. Akselrod, E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5981829]
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| − | * Vinayak Gokhale, Jonghoon Jin, Aysegul Dundar, Berin Martini and Eugenio Culurciello, "A 240 G-ops/s Mobile Coprocessor for Deep Neural Networks", Proc. IEEE CVPRW'14 [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6910056]
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| − | and a not-yet-published paper of our group.
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| − | <!-- F. Conti, L. Benini, "A Ultra-Low-Energy Convolution Engine for Fast Brain-Inspired Vision in Multicore Clusters", submitted to IEEE DAC'15, under review. -->
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| | ===Practical Details=== | | ===Practical Details=== |
| | * '''[[Project Plan]]''' | | * '''[[Project Plan]]''' |
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| | ==Results== | | ==Results== |
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| − | ==Links==
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| − | * The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]
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| − | * The IIS/DZ coding guidelines [http://www.dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html]
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| − | [[#top|↑ top]]
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| − | [[Category:Digital]]
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| − | [[Category:In progress]]
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| − | [[Category:Semester Thesis]]
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| − | <!--
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| − | COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES
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| − | GROUP
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| − | [[Category:Digital]]
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| − | [[Category:Analog]]
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| − | [[Category:Nano-TCAD]]
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| − | [[Category:Nano Electronics]]
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| − | STATUS
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| − | [[Category:Available]]
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| − | [[Category:In progress]]
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| − | [[Category:Completed]]
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| − | [[Category:Hot]]
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| − | TYPE OF WORK
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| − | [[Category:Semester Thesis]]
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| − | [[Category:Master Thesis]]
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| − | [[Category:PhD Thesis]]
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| − | [[Category:Research]]
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| − | NAMES OF EU/CTI/NT PROJECTS
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| − | [[Category:UltrasoundToGo]]
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| − | [[Category:IcySoC]]
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| − | [[Category:PSocrates]]
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| − | [[Category:UlpSoC]]
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| − | [[Category:Qcrypt]]
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| − | YEAR (IF FINISHED)
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| − | [[Category:2010]]
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| − | [[Category:2011]]
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| − | [[Category:2012]]
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| − | [[Category:2013]]
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| − | [[Category:2014]]
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| − | --->
| + | [[Category:Hot]] [[Category:Digital]] [[Category:Master Thesis]] [[Category:Available]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:SBB CHCRC]] [[Category:Model Predictive Controller]] |
QP problems arise in various embedded optimization applications such as model predictive control or constrained least-square fitting. Various solution algorithms have been proposed and implemented on CPUs (some of them also on FPGAs), each of them exhibiting specific advantages and drawbacks. Active-set methods are frequently used on CPUs for solving QPs efficiently, but their use on FPGAs is considered challenging as they rely on more involved linear algebra operations such as matrix factorizations. Aim of this thesis project is to investigate the potential of implementing an active-set method for FPGAs and to identify/adapt an existing scheme to be implemented in hardware.
