View source for LightProbe - Design of a High-Speed Optical Link

[[File:LP-firmware.png|thumb|600px]]

== Short Description ==
In the [[LightProbe]] project, we are exploring the next generation of medical ultrasound imaging systems: The LightProbe is a programmable ultrasound transducer head, which incorporates the entire analog frontend and directly outputs the captured digital samples. This allows the LightProbe to be directly connected to any commodity hardware (phone, tablet, workstation) for post-processing over a standard digital link as simple as a standard peripheral, like a camera.

The LightProbe has two main challenges: The involved ten's of Gb/s data-rates produced by the frontend, which need to be processed and transported off-head, and the power/thermal constraints of such a high-performance handheld device. 

At full operation the frontend produces a digital stream of several Gbit per second. In order to transport this data-rate efficiently from the head to the backend processing system, we use a optical high-speed link.

The goal of this project is to implement this optical link between two FPGAs and design the higher level communication protocol running on that link. To achieve multi Gbit/s datarates you will use the GTP/GTX Transceivers, which can be found has hard IPs on state-of-the art FPGAs. These transceiver can achieve 6.6Gb/s and 16.3Gb/s respectively over a single LVDS pair or one optical fiber channel.


== Tasks ==
[[File:LPi-optical.jpg|thumb|400px]]
You will work with our prototype custom FPGA board (see Picture) and a Kintex Ultrascale board from Xilinx.
You will be given two running (and tested!) dummy projects (one for each board), with the most basic link working. 
Your tasks are
* Building the complete link including the required infrastructure on both sides.
* Come up with your own higher level communication protocol and implement it.
* Test and measure the speed you can achieve over your link using your protocol.

This is an advanced FPGA project and ideal if you want to master more complex FPGA design, which extensively use both hard and software IPs. Using these IPs allows to build rather easily very complex system. You will be extensively working with the Xilinx Vivado Tool.


=== Prerequisites ===
* VLSI I
* Basic C

===Status: Available ===
: Looking for Interested Students
: Supervision: [[:User:Phager|Pascal Hager]]

===Character===
: 10% Preparations - understand given projects
: 30% Implementation of the link
: 50% Protocol design and test
: 10% Measurements


===Professor===
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]
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[[Category:Digital]]
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[[Category:Semester Thesis]]
[[Category:UltrasoundToGo]]
[[Category:Phager]]
[[Category:System Design]]
[[Category:FPGA]]