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| − | [[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]
| + | This site is currently being created. Please stay tuned, more information will be uploaded shortly. |
| − | ==Short Description==
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| − | Jamming attacks pose a critical threat to wireless communication systems. Multi-antenna (MIMO) wireless systems have the potential to mitigate such jamming attacks through signal processing. Methods for jammer mitigation are thus currently a hot research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms have been proposed. To be practically viable, such methods will ultimately have to be implemented in hardware (using FPGAs or, more likely, ASICs), since sofware-based signal processing will never support the data rates of modern wireless systems. To this date, however, there are no hardware implementations of jammer mitigation algorithms.
| + | Contact: Reinhard Wiesmayr |
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| − | The goal of this project is to develop the first ASIC implementation of a jammer-mitigating signal processing algorithm. For this, the student will take a state-of-the art jammer mitigation algorithm and adapt it as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology.
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| − | [1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient communication using MIMO interference cancellation." IEEE Transactions on Information Forensics and Security 11(7), 2016, 1486-1499.
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| − | [2] H. Akhlaghpasand, E. Björnson, and S. Mohammad Razavizadeh. "Jamming suppression in massive MIMO systems." IEEE Transactions on Circuits and Systems II: Express Briefs 67(1), 2019, 182-186.
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| − | [3] T. Erpek, Y. E. Sagduyu, and Y. Shi. "Deep learning for launching and mitigating wireless jamming attacks." IEEE Transactions on Cognitive Communications and Networking 5(1), 2018, 2-14.
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| − | ===Status: Available ===
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| − | : Looking for 1-2 Semester/Master students
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| − | : Contact: [https://iip.ethz.ch/people/profiles.MzAxMjAz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Reinhard Wiesmayr]
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| − | | |
| − | ===Prerequisites===
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| − | : Verilog or VHDL
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| − | : VLSI II
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| − | : Familiarity with the basics of digital communication is recommended but not strictly required
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| − | <!--
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| − | ===Status: Completed ===
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| − | : Fall Semester 2014 (sem13h2)
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| − | : Matthias Baer, Renzo Andri
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| − | --->
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| − | <!--
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| − | ===Status: In Progress ===
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| − | : Student A, StudentB
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| − | : Supervision: [[:User:Mluisier | Mathieu Luisier]]
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| − | --->
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| − | ===Character===
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| − | : 80% VLSI Implementation and Verification
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| − | : 20% MATLAB simulation
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| − | ===Professor===
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| − | <!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] --->
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| − | <!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] --->
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| − | <!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] --->
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| − | <!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] --->
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| − | : [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]
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| − | <!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] --->
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| − | [[#top|↑ top]]
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| − | ==Detailed Task Description==
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| − | | |
| − | ===Goals===
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| − | ===Practical Details===
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| − | * '''[[Project Plan]]'''
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| − | * '''[[Project Meetings]]'''
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| − | * '''[[Design Review]]'''
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| − | * '''[[Coding Guidelines]]'''
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| − | * '''[[Final Report]]'''
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| − | * '''[[Final Presentation]]'''
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| − | ==Results==
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| − | ==Links==
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| − | [[Category:Available]]
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| − | [[Category:IIP]]
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| − | [[Category:IIP_5G]]
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| − | [[#top|↑ top]]
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| − | <!--
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| − | COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES
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| − | GROUP
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| − | [[Category:cat2]]
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| − | [[Category:cat3]]
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| − | [[Category:Digital]]
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| − | SUB CATEGORIES
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| − | NEW CATEGORIES
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| − | [[Category:Computer Architecture]]
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| − | [[Category:SmartSensors]]
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| − | [[Category:Transient Computing]]
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| − | [[Category:System on Chips for IoTs]]
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| − | [[Category:Energy Efficient Autonomous UAVs]]
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| − | [[Category:Biomedical System on Chips]]
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| − | [[Category:Digital Medical Ultrasound Imaging]]
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| − | [[Category:Deep Learning Acceleration]]
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| − | [[Category:Competition]]
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| − | [[Category:ASIC]]
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| − | [[Category:FPGA]]
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| − | [[Category:System Design]]
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| − | [[Category:Processor]]
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| − | STATUS
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| − | TYPE OF WORK
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| − | [[Category:Group Work]]
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| − | [[Category:Semester Thesis]]
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| − | [[Category:Master Thesis]]
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| − | [[Category:PhD Thesis]]
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| − | [[Category:Research]]
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| − | NAMES OF EU/CTI/NT PROJECTS
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| − | [[Category:Fractal]]
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| − | YEAR (IF FINISHED)
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| − | [[Category:2010]]
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| − | --->
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This site is currently being created. Please stay tuned, more information will be uploaded shortly.
