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Difference between revisions of "Low-Power Time Synchronization for IoT Applications"

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: 50% Algorithm development in MATLAB
 
: 50% Algorithm development in MATLAB
 
: 50% Asynchronous VLSI design with System Verilog
 
: 50% Asynchronous VLSI design with System Verilog
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==Detailed Task Description==
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===Goals===
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===Practical Details===
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* '''[[Project Plan]]'''
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* '''[[Project Meetings]]'''
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* '''[[Design Review]]'''
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* '''[[Coding Guidelines]]'''
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* '''[[Final Report]]'''
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* '''[[Final Presentation]]'''
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==Results==
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==Links==
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[[Category:Available]]
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[[Category:IIP]]
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[[Category:IIP_5G]]
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Latest revision as of 12:34, 25 May 2022

Short Description

Wireless receivers need to estimate the time instant when data is transmitted as otherwise entire data packets are lost. Thus, accurate time synchronization is essential for reliable communication. The goal of this project is to develop a novel synchronization algorithm for multi-antenna wireless systems and implement it in hardware while minimizing area and power.

Status: Available

Looking for 1-2 Semester/Master students
Contact: Darja Nonaca, dnonaca@iis.ee.ethz.ch

Prerequisites

Communication Systems (or a similar course)
VLSI 1
VLSI 3 (recommended)