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[[Category:Digital]]
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[[Category:ASIC]]
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[[Category:Computer and System Architecture]]
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[[Category:Hot]]
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[[Category:High Performance Computing]]
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[[Category:FPGA & Digital ASIC Design]]
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[[Category:Energy Efficient SoCs]]
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[[Category:2022]]
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[[Category:Master Thesis]]
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[[Category:Pschiavo]]
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[[Category:Meggiman]]
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[[Category:Available]]
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== Status: Available ==
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* Type: Semester or Master Thesis
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* Professor: Prof. Dr. L. Benini
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* Supervisors:
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** [[:User:Pschiavo | Pasquale Davide Schiavone]]
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** [[:User:Meggiman | Manuel Eggimann]] : [mailto:meggimann@iis.ee.ethz.ch meggimann@iis.ee.ethz.ch]
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==Introduction==
 
==Introduction==
  
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The project will be carried out at the IIS laboratory at ETH, one of the world's top-class universities, under the supervision of Prof. Luca Benini and Dr. Davide Schiavone.
 
The project will be carried out at the IIS laboratory at ETH, one of the world's top-class universities, under the supervision of Prof. Luca Benini and Dr. Davide Schiavone.
 +
 +
==Project objectives==
 +
 +
* Understanding the X-HEEP and PULP microcontrollers, how they works, and learning how IPs are integrated. Understand how the configuration script of the bus and CPU is implemented.
 +
* Understanding the memories building blocks modules of MCUs and how to connect them.
 +
* Understanding the bus building blocks modules of MCUs and how to connect them.
 +
* Building python scripts to generate the SystemVerilog files that implement the user’s memory and bus selected topology.
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* Validation of the built MCU generator with C tests.
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* Analysis of the performance of the different bus and memory architectures over a set of applications.
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 +
Do not worry, the work it is not done twice, most of the IPs are actually the same.
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==Required Skills==
 +
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To work on this project, you will need:
 +
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) - having followed the VLSI1 / VLSI2 courses is recommended
 +
* to have prior knowledge of hardware design and python
 +
* to have scientific curiosity
 +
* to have good communication skills and to know English
 +
 +
Other skills that you might find useful include:
 +
* familiarity with a scripting language
 +
* to be strongly motivated for a super-cool project
 +
 +
If you want to work on this project, but you think that you do not match some the required skills, we can give you some preliminary exercise to help you fill in the gap.
 +
 +
==Contact Information==
 +
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Contact Davide Schiavone davide.schiavone@epfl.ch or pschiavo@iis.ee.ethz.ch
 +
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===Professor===
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: [https://ee.ethz.ch/the-department/people-a-z/person-detail.luca-benini.html Luca Benini]
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[[#top|↑ top]]
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===Meetings & Presentations===
 +
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.
 +
 +
Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [http://eda.ee.ethz.ch/index.php/Design_review].

Latest revision as of 12:45, 18 August 2022



Status: Available


Introduction

Microcontrollers (MCUs) are used in a wide range of applications ranging from sensor-monitoring all the way to robotics. Despite typically lower in performance, they are usually preferred over custom circuits and FPGAs thanks to their versatility and easy programmability via software routines typically written in the C language. STMicroelectronics, SiLabs, NXP, Raspberry, and Arduino are probably the most used ones. These vendors provide different flavors of microcontrollers that optimize different angles, such as power, cost, performance, functionalities, and software stack, which is typically either based on real-time operating systems. To be able to customize the computer architecture of those microcontrollers, if possible at all, the users must buy expensive licenses from the providers for the rights of customizing and selling their own IPs. Differently, the Linux revolution made the software business wider and more competitive as much of the software is open source and free to be customized. Linux, Android, freeRTOS, GCC, and LLVM are just a few examples of the most used software in the microcontroller markets However, in recent years, open-source hardware is becoming a key trend that is changing how the chip industry works. It all started with the open source instruction set architecture RISC-V, which was followed by many IPs described in Verilog or VHDL on Github or other servers, all the way to the foundation of worldwide organizations that maintain, develop, and verify industrial-grade open source processors and microcontrollers as for example the OpenHW Group and LowRISC, whose IPs are used in industrial-products freely, without the need of paying any fee or license. Switzerland, thanks to ETH Zurich, plays a big role in this picture as one of the main providers of those IPs coming from the PULP project that eventually end up first being verified by the aforementioned foundations, then being implemented in products. Also, the Embedded Systems Laboratory (ESL) at the Ecole Polytechnique Fédérale de Lausanne (EPFL) is developing an open-source RISC-V-based microcontroller called x-heep, which shares most of the IPs with the ETH's PULP system.

Project description

Our idea is to provide high-level customization to our RISC-V MCUs (pulp and x-heep) by providing tools to configure the MCU to the users' needs, in a friendly way, making it de-facto a microcontroller generator. In particular, we want to make the bus and the memory subsystem of our systems configurable at design time. To build a such generator, the student will use python (e.g., Mako templates) and SystemVerilog for generating the memory and the bus subsystem starting from user-specified configurations (e.g. in JSON format). The project focuses on extending the bus topology choice and the memory size and topology. The user should be able to specify the on-chip RAM size, the number of banks the RAM is made of, and the cut size. The user should also be able to specify the bus topology, the number of masters that can access the bus concurrently, the number of slaves that can be accessed concurrently, and whether master-to-slave specific paths are broken with FIFOs to improve timing and area. In addition, the user should choose how many ports each slave gives access to the masters (e.g., 1 port from the SPI, 4 ports from memory, etc.), and whether the access is given in continuous addressing mode, or interleaved addressing mode. For example, if a memory exposes 4 access ports to the masters, the ports are used in a contiguous way if the address from base to base+offset goes to port 0, from base+offset to base+2 * offset to port 1, etc. Whereas the ports are used interleaved if the base address goes to port 0, base+1 to port 1, ..., base+4 to port0 again, etc. The user will specify the configuration in a JSON file to tell the python script how to generate the HDL files.

Throughout the project, the student will learn:

  • 1. How to design and implement different memory subsystems in terms of numbers of ports/banks (bandwidth), and numbers of cuts (size of memory the bank is made of, e.g., 1 bank of 32kB can be done with 1 cut of 32kB, 2 cuts of 16kB or 4 cuts of 8KB, etc.).
  • 2. How to design and implement different bus topologies in terms of numbers of masters that can access concurrently the bus, numbers of slaves directly connected to the bus (slave latency), and for multiple-ports memory slaves, addressing mode (contiguous or interleaved).
  • 3. How to integrate such new IPs and their generator in the x-heep and pulp open-source RISC-V microcontrollers.
  • 4. How to analyze how the selected topologies and memory architectures impact the performance of the microcontroller on a set of applications (e.g. matrix multiplication, convolution, ADC sampling).
  • 5. How to work with git repositories and in a team of people all contributing to the same project.

The project will be carried out at the IIS laboratory at ETH, one of the world's top-class universities, under the supervision of Prof. Luca Benini and Dr. Davide Schiavone.

Project objectives

  • Understanding the X-HEEP and PULP microcontrollers, how they works, and learning how IPs are integrated. Understand how the configuration script of the bus and CPU is implemented.
  • Understanding the memories building blocks modules of MCUs and how to connect them.
  • Understanding the bus building blocks modules of MCUs and how to connect them.
  • Building python scripts to generate the SystemVerilog files that implement the user’s memory and bus selected topology.
  • Validation of the built MCU generator with C tests.
  • Analysis of the performance of the different bus and memory architectures over a set of applications.

Do not worry, the work it is not done twice, most of the IPs are actually the same.

Required Skills

To work on this project, you will need:

  • to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) - having followed the VLSI1 / VLSI2 courses is recommended
  • to have prior knowledge of hardware design and python
  • to have scientific curiosity
  • to have good communication skills and to know English

Other skills that you might find useful include:

  • familiarity with a scripting language
  • to be strongly motivated for a super-cool project

If you want to work on this project, but you think that you do not match some the required skills, we can give you some preliminary exercise to help you fill in the gap.

Contact Information

Contact Davide Schiavone davide.schiavone@epfl.ch or pschiavo@iis.ee.ethz.ch

Professor

Luca Benini

↑ top

Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].