Revision as of 17:26, 1 March 2023

On this page, you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.

Institute Organization

The IIS Consists of 7 main research groups

• Analog and Mixed Signal Design
• Digital Circuits and Systems
• Energy Efficient Circuits and IoT Systems
• Nano-TCAD
• Integrated Information Processing
• Physical Characterization
• Integrated Devices, Electronics, And Systems

Integrated Devices, Electronics, And Systems Group (Prof. Wang)

• Simulation of 2D artificial cilia metasurface in COMSOL
• An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
• Noise Figure Measurement for Cryogenic System
• Design of a D-Band Variable Gain Amplifier for 6G Communication
• Super Resolution Radar/Imaging at mm-Wave frequencies
• Machine Learning Assisted Direct Synthesis of Passive Networks
• High resolution, low power Sigma Delta ADC
• Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening

Analog and Mixed Signal Design Group (Dr. Burger)

• Analog IC Design
• Mixed Signal IC Design
• Wireless Communication Systems for the IoT
  • Wearables for Sports and Fitness Tracking
• Cryptographic Hardware
• Deep Learning Acceleration
• IBM Research
• Huawei Research

Energy Efficient Circuits and IoT Systems Group (Prof. Jang)

• Neural Recording Interface and Spike Sorting Algorithm
• Design of Streaming Data Platform for High-Speed ADC Data
• Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
• An Ultra-Low-Power Neuromorphic Spiking Neuron Design
• Energy Efficient Serial Link
• Design of low mismatch DAC used for VAD
• Development of an implantable Force sensor for orthopedic applications
• Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
• Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
• Hardware/software codesign neural decoding algorithm for “neural dust”
• Application Specific Frequency Synthesizers (Analog/Digital PLLs)

Nano-TCAD Group (Prof. Luisier)

• Efficient Banded Matrix Multiplication for Quantum Transport Simulations
• Charge and heat transport through graphene nanoribbon based devices
• Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
• Quantum Transport Modeling of Interband Cascade Lasers (ICL)
• Every individual on the planet should have a real chance to obtain personalized medical therapy
• Integrated silicon photonic structures-Lumiphase
• Characterization techniques for silicon photonics-Lumiphase
• Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
• Electrothermal characterization of van der Waals Heterostructures with a partial overlap
• Phase-change memory devices for emerging computing paradigms
• Finite element modeling of electrochemical random access memory
• Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
• Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
• Quantum transport in 2D heterostructures
• Development of an efficient algorithm for quantum transport codes
• Investigation of Metal Diffusion in Oxides for CBRAM Applications
• Investigation of Redox Processes in CBRAM

Integrated Information Processing Group (Prof. Studer)

• ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
• Artificial Reverberation for Embedded Systems
• High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
• High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
• Modular Frequency-Modulation (FM) Music Synthesizer
• Alias-Free Oscillator Synchronization for Arbitrary Waveforms
• Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
• Low-Complexity MIMO Detection
• Low-power time synchronization for IoT applications
• Forward error-correction ASIC using GRAND
• Through Wall Radar Imaging using Machine Learning
• Passive Radar for UAV Detection using Machine Learning
• Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication
• Digitally-Controlled Analog Subtractive Sound Synthesis
• Low Resolution Neural Networks
• Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
• XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
• VLSI Design of an Asynchronous LDPC Decoder
• FFT HDL Code Generator for Multi-Antenna mmWave Communication
• Deep Unfolding of Iterative Optimization Algorithms
• Low-Resolution 5G Beamforming Codebook Design
• Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
• Practical Reconfigurable Intelligent Surfaces (RIS)
• Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
• Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
• Peak-to-average power Reduction

Physical Characterization Group (Dr.Ciappa)

• Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
• Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
• Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
• Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
• Design and implementation of the front-end for a portable ionizing radiation detector

Collaborations with other groups/departments

• Real-Time Implementation of Quantum State Identification using an FPGA

Selected Projects in Progress

For a complete list, see Projects in Progress.

• ASR-Waveformer
• GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
• A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
• Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
• Fault-Tolerant Floating-Point Units (M)

Selected Completed Projects

For a complete list, see Completed Projects.

• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
• Exploring NAS spaces with C-BRED
• Bandwidth Efficient NEureka
• Feature Extraction and Architecture Clustering for Keyword Spotting (1S)

Selected Research Projects

For a complete list, see Research Projects.

• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
• Exploring NAS spaces with C-BRED
• Bandwidth Efficient NEureka
• Feature Extraction and Architecture Clustering for Keyword Spotting (1S)

Links to Other IIS Webpages

http://www.iis.ee.ethz.ch

Integrated Systems Laboratory Main homepage

http://www.nano-tcad.ethz.ch

Nano-TCAD group homepage

http://www.dz.ee.ethz.ch

Microelectronics Design Center

http://asic.ethz.ch/cg

The IIS-ASIC Chip Gallery

http://eda.ee.ethz.ch

EDA Wiki (ETH Zurich internal access only!)