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Revision as of 12:43, 9 February 2015
Welcome to IIS-Projects
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Institute Organization
The IIS Consists of 4 main research groups
- Analog and Mixed Signal Design
- IC and Systems, Design and Test
- Nano Electronics and Nano Photonics
- Nano-TCAD
Available Hot Student Projects
For a complete list, see Available Projects.
Analog Design
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Digital Design
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Exploring NAS spaces with C-BRED
- Bridging QuantLab with LPDNN
- Improved Collision Avoidance for Nano-drones
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
Nano Electronics
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
Nano-TCAD
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Integrated silicon photonic structures-Lumiphase
- Characterization techniques for silicon photonics-Lumiphase
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
Selected Projects in Progress
For a complete list, see Projects in Progress.
- Design of combined Ultrasound and Electromyography systems
- Streaming Integer Extensions for Snitch (M/1-2S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Novel Metastability Mitigation Technique
Selected Completed Projects
For a complete list, see Completed Projects.
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Triple-Core PULPissimo
- Watchdog Timer for PULP
Selected Research Projects
For a complete list, see Research Projects.
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Triple-Core PULPissimo
- Watchdog Timer for PULP
Links to Other IIS Webpages
- http://www.iis.ee.ethz.ch
- Integrated Systems Laboratory Main homepage
- http://lne.ee.ethz.ch
- Laboratory for Nanoelectronics homepage
- http://www.nano-tcad.ethz.ch
- Nano-TCAD group homepage
- http://www.dz.ee.ethz.ch
- Microelectronics Design Center
- http://asic.ethz.ch/cg
- The IIS-ASIC Chip Gallery
- http://eda.ee.ethz.ch
- EDA Wiki (ETH Zurich internal access only!)
