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Revision as of 11:43, 9 February 2015
Welcome to IIS-Projects
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Institute Organization
The IIS Consists of 4 main research groups
- Analog and Mixed Signal Design
- IC and Systems, Design and Test
- Nano Electronics and Nano Photonics
- Nano-TCAD
Available Hot Student Projects
For a complete list, see Available Projects.
Analog Design
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Digital Design
- Smart e-glasses for concealed recording of EEG signals
- Fast Accelerator Context Switch for PULP
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Visualization of Neural Architecture Search Spaces
- Wireless EEG Acquisition and Processing
Nano Electronics
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
Nano-TCAD
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Integrated silicon photonic structures-Lumiphase
- Characterization techniques for silicon photonics-Lumiphase
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
Selected Projects in Progress
For a complete list, see Projects in Progress.
- Designing a Power Management Unit for PULP SoCs
- Implementing DSP Instructions in Banshee (1S)
- Analog Compute-in-Memory Accelerator Interface and Integration
- Cell-Free mmWave Massive MIMO Communication
- Ultra low power wearable ultrasound probe
Selected Completed Projects
For a complete list, see Completed Projects.
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Hardware Constrained Neural Architechture Search
- Implementation of an AES Hardware Processing Engine (B/S)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Transforming MemPool into a CGRA (M)
Selected Research Projects
For a complete list, see Research Projects.
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Hardware Constrained Neural Architechture Search
- Implementation of an AES Hardware Processing Engine (B/S)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Transforming MemPool into a CGRA (M)
Links to Other IIS Webpages
- http://www.iis.ee.ethz.ch
- Integrated Systems Laboratory Main homepage
- http://lne.ee.ethz.ch
- Laboratory for Nanoelectronics homepage
- http://www.nano-tcad.ethz.ch
- Nano-TCAD group homepage
- http://www.dz.ee.ethz.ch
- Microelectronics Design Center
- http://asic.ethz.ch/cg
- The IIS-ASIC Chip Gallery
- http://eda.ee.ethz.ch
- EDA Wiki (ETH Zurich internal access only!)
