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Revision as of 12:46, 9 February 2015
Welcome to IIS-Projects
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Institute Organization
The IIS Consists of 4 main research groups
- Analog and Mixed Signal Design
- IC and Systems, Design and Test
- Nano Electronics and Nano Photonics
- Nano-TCAD
Available Hot Student Projects
For a complete list, see Available Projects.
Analog Design
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Digital Design
- Integration Of A Smart Vision System
- Event-based navigation on autonomous nano-drones
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Exploring NAS spaces with C-BRED
- Bridging QuantLab with LPDNN
- Improved Collision Avoidance for Nano-drones
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Smart e-glasses for concealed recording of EEG signals
- Fast Accelerator Context Switch for PULP
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Visualization of Neural Architecture Search Spaces
- Wireless EEG Acquisition and Processing
- Self Aware Epilepsy Monitoring
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Non-blocking Algorithms in Real-Time Operating Systems
- CLIC for the CVA6
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Probing the limits of fake-quantised neural networks
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Fast Simulation of Manycore Systems (1S)
- Ternary Neural Networks for Face Recognition
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Evaluating SoA Post-Training Quantization Algorithms
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Huawei Research
- Graph neural networks for epileptic seizure detection
- IBM Research
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Data Augmentation Techniques in Biosignal Classification
- Compression of iEEG Data
- BCI-controlled Drone
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Deep neural networks for seizure detection
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Real-Time Implementation of Quantum State Identification using an FPGA
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- PVT Dynamic Adaptation in PULPv3
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Using Motion Sensors to Support Indoor Localization
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
Nano Electronics
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
Nano-TCAD
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Integrated silicon photonic structures-Lumiphase
- Characterization techniques for silicon photonics-Lumiphase
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Phase-change memory devices for emerging computing paradigms
- Finite element modeling of electrochemical random access memory
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Quantum transport in 2D heterostructures
- Development of an efficient algorithm for quantum transport codes
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Redox Processes in CBRAM
Selected Projects in Progress
For a complete list, see Projects in Progress.
- SCMI Support for Power Controller Subsystem
- Design of combined Ultrasound and Electromyography systems
- Streaming Integer Extensions for Snitch (M/1-2S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- Novel Metastability Mitigation Technique
Selected Completed Projects
For a complete list, see Completed Projects.
- PULP’s CLIC extensions for fast interrupt handling
- Cell-Free mmWave Massive MIMO Communication
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
Selected Research Projects
For a complete list, see Research Projects.
- PULP’s CLIC extensions for fast interrupt handling
- Cell-Free mmWave Massive MIMO Communication
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
Links to Other IIS Webpages
- http://www.iis.ee.ethz.ch
- Integrated Systems Laboratory Main homepage
- http://lne.ee.ethz.ch
- Laboratory for Nanoelectronics homepage
- http://www.nano-tcad.ethz.ch
- Nano-TCAD group homepage
- http://www.dz.ee.ethz.ch
- Microelectronics Design Center
- http://asic.ethz.ch/cg
- The IIS-ASIC Chip Gallery
- http://eda.ee.ethz.ch
- EDA Wiki (ETH Zurich internal access only!)
