Difference between revisions of "Main Page"
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| + | <CENTER><H1> Welcome to IIS-Projects</H1></CENTER> | ||
In this page you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich]. | In this page you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich]. | ||
| − | + | The IIS Consists of 4 main research groups | |
| + | * [[:Category:Analog| Analog and Mixed Signal Design]] | ||
| + | * [[:Category:Digital| IC and Systems, Design and Test]] | ||
| + | * [[:Category:Nano Electronics| Nano Electronics and Nano Photonics]] | ||
| + | * [[:Category:Nano-TCAD|Nano-TCAD]] | ||
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| + | On this webpage you can find links to | ||
| + | * [[:Category:Available| Projects for which we are looking for students]] | ||
| + | * [[:Category:Completed| Projects that have been completed in the past]] | ||
| + | * [[:Category:Research| List of Research projects]] | ||
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==Projects in Progress== | ==Projects in Progress== | ||
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category = Digital | category = Digital | ||
category = In progress | category = In progress | ||
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Revision as of 17:41, 30 January 2014
Welcome to IIS-Projects
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
The IIS Consists of 4 main research groups
- Analog and Mixed Signal Design
- IC and Systems, Design and Test
- Nano Electronics and Nano Photonics
- Nano-TCAD
On this webpage you can find links to
- Projects for which we are looking for students
- Projects that have been completed in the past
- List of Research projects
Projects in Progress
Digital Design
- ASR-Waveformer
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Fault-Tolerant Floating-Point Units (M)
- Efficient collective communications in FlooNoC (1M)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Streaming Layer Normalization in ITA (M/1-2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Physical Implementation of ITA (2S)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Ultrasound-EMG combined hand gesture recognition
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- Implementation of a Cache Reliability Mechanism (1S/M)
- On - Device Continual Learning for Seizure Detection on GAP9
- On-Board Software for PULP on a Satellite
- Big Data Analytics Benchmarks for Ara
- Radiation Testing of a PULP ASIC
- Virtual Memory Ara
- Runtime partitioning of L1 memory in Mempool (M)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- Zephyr RTOS on PULP
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Ultrasound Doppler system development
- New RVV 1.0 Vector Instructions for Ara
- Ternary Neural Networks for Face Recognition
- ASIC Development of 5G-NR LDPC Decoder
- Efficient TNN compression
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Event-Driven Vision on an embedded platform
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
