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Revision as of 15:33, 16 January 2014

Welcome to the IIS Projects page

In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.

• A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
• Battery indifferent wearable Ultrasound
• Design of combined Ultrasound and Electromyography systems
• Wearable Ultrasound for Artery monitoring
• Ultrasound Doppler system development
• Exploring NAS spaces with C-BRED
• Bridging QuantLab with LPDNN
• Machine Learning for extracting Muscle features from Ultrasound raw data
• Improved Collision Avoidance for Nano-drones
• Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
• Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
• New RVV 1.0 Vector Instructions for Ara
• User:Prasadar
• Triple-Core PULPissimo
• Deep Learning-based Global Local Planner for Autonomous Nano-drones
• Ultra-wideband Concurrent Ranging
• Smart e-glasses for concealed recording of EEG signals
• Development of a fingertip blood pressure sensor
• Fast Accelerator Context Switch for PULP
• PULP’s CLIC extensions for fast interrupt handling
• Neural Architecture Search using Reinforcement Learning and Search Space Reduction
• Visualization of Neural Architecture Search Spaces
• Wireless EEG Acquisition and Processing
• Self Aware Epilepsy Monitoring
• Enhancing our DMA Engine with Fault Tolerance
• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
• Watchdog Timer for PULP
• Serverless Benchmarks on RISC-V (M)
• Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
• Designing a Power Management Unit for PULP SoCs
• SCMI Support for Power Controller Subsystem
• Streaming Integer Extensions for Snitch (M/1-2S)
• Implementing DSP Instructions in Banshee (1S)
• A Unified Compute Kernel Library for Snitch (1-2S)
• Non-blocking Algorithms in Real-Time Operating Systems
• User:Fischeti
• Adding Linux Support to our DMA Engine (1-2S/B)
• Counter-based Fast Power Estimation using FPGAs (M/1-3S)
• Integrating Hardware Accelerators into Snitch (1S)
• Flexfloat DL Training Framework
• CLIC for the CVA6
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
• Mixed-Precision Neural Networks for Brain-Computer Interface Applications
• Ultra low power wearable ultrasound probe
• Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
• Feature Extraction for Speech Recognition (1S)
• Probing the limits of fake-quantised neural networks
• Analog Compute-in-Memory Accelerator Interface and Integration
• Machine Learning for extracting Muscle features using Ultrasound 2
• EEG artifact detection with machine learning
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
• EEG artifact detection for epilepsy monitoring
• Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
• Fast Simulation of Manycore Systems (1S)
• User:Vladn
• Ternary Neural Networks for Face Recognition
• Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
• Evaluating SoA Post-Training Quantization Algorithms
• Hardware/software codesign neural decoding algorithm for “neural dust”
• Novel Metastability Mitigation Technique
• Automatic unplugging detection for Ultrasound probes
• Ultrasound Low power WiFi with IMX7
• Ultrasound signal processing acceleration with CUDA
• Compression of Ultrasound data on FPGA
• Ibex: Tightly-Coupled Accelerators and ISA Extensions
• Huawei Research
• Implementation of an AES Hardware Processing Engine (B/S)
• Securing Block Ciphers against SCA and SIFA
• Graph neural networks for epileptic seizure detection
• Online Learning of User Features (1S)
• Wearables in Fashion
• Efficient TNN Inference on PULP Systems
• Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
• Implementing A Low-Power Sensor Node Network
• LLVM and DaCe for Snitch (1-2S)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• Heroino: Design of the next CORE-V Microcontroller
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
• Transforming MemPool into a CGRA (M)
• Manycore System on FPGA (M/S/G)
• Bluetooth Low Energy receiver in 65nm CMOS
• RVfplib
• Efficient Synchronization of Manycore Systems (M/1S)
• Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• Short Range Radars For Biomedical Application
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Matheus Cavalcante
• Smart Patch For Heath Care And Rehabilitation
• Autonomus Drones With Novel Sensors And Ultra Wide Band
• Evaluating memory access pattern specializations in OoO, server-grade cores (M)
• Evaluating An Ultra low Power Vision Node
• Hypervisor Extension for Ariane (M)
• Mapping Networks on Reconfigurable Binary Engine Accelerator
• Biomedical Circuits, Systems, and Applications
• User:Thoriri
• User:Georg
• Probabilistic training algorithms for quantized neural networks
• Exploring schedules for incremental and annealing quantization algorithms
• User:Susman
• ASIC Development of 5G-NR LDPC Decoder
• VLSI Implementation of a 5G Ciphering Accelerator
• Machine Learning on Ultrasound Images
• Low Latency Brain-Machine Interfaces
• IP-Based SoC Generation and Configuration (1-3S/B)
• Efficient TNN compression
• ISA extensions in the Snitch Processor for Signal Processing (M)
• MemPool on HERO (1S)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• Multi issue OoO Ariane Backend (M)
• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• PREM Runtime Scheduling Policies
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• User:Mmaxim
• User:Scheremo
• Event-Driven Vision on an embedded platform
• Smart Meters
• User:Lbertaccini
• Time Gain Compensation for Ultrasound Imaging
• Minimum Variance Beamforming for Wearable Ultrasound Probes
• Machine Learning for extracting Muscle features using Ultrasound
• Knowledge Distillation for Embedded Machine Learning
• Hardware Constrained Neural Architechture Search
• IBM Research
• Hyper-Dimensional Computing Based Predictive Maintenance
• Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
• Memory Augmented Neural Networks in Brain-Computer Interfaces
• User:Meggiman
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
• RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
• Improved State Estimation on PULP-based Nano-UAVs
• Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
• Data Augmentation Techniques in Biosignal Classification
• Compression of iEEG Data
• BCI-controlled Drone
• Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
• Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
• Real-Time Motor-Imagery Classification Using Neuromorphic Processor
• Accurate deep learning inference using computational memory
• Deep neural networks for seizure detection
• Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
• Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
• User:Sriedel
• Ibex: Bit-Manipulation Extension
• Ibex: FPGA Optimizations
• Spiking Neural Network for Autonomous Navigation
• Event-Driven Convolutional Neural Network Modular Accelerator
• Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
• Design of an Ultra-Reliable Low-Latency Modem
• Satellite Internet of Things
• An Energy Efficient Brain-Computer Interface using Mr.Wolf
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
• TCNs vs. LSTMs for Embedded Platforms
• Exploring Algorithms for Early Seizure Detection
• Improving Resiliency of Hyperdimensional Computing
• Toward Superposition of Brain-Computer Interface Models
• Towards global Brain-Computer Interfaces
• Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
• Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
• High-throughput Embedded System For Neurotechnology in collaboration with INI
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
• Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
• Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
• Visualizing Functional Microbubbles using Ultrasound Imaging
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
• User:Matheusd
• Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
• Next Generation Synchronization Signals
• Extending the RISCV backend of LLVM to support PULP Extensions
• Compiler Profiling and Optimizing
• PREM Intervals and Loop Tiling
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
• FPGA Testbed Implementation for Bluetooth Indoor Positioning
• Subject specific embeddings for transfer learning in brain-computer interfaces
• Channel Estimation for 5G Cellular IoT and Fast Fading Channels
• User:Paulin
• User:Herschmi
• Deep Convolutional Autoencoder for iEEG Signals
• LightProbe - CNN-Based-Image-Reconstruction
• LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
• Floating-Point Divide & Square Root Unit for Transprecision
• Level Crossing ADC For a Many Channels Neural Recording Interface
• LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
• Herschmi
• Developing a small portable neutron detector for detecting smuggled nuclear material
• Timing Channel Mitigations for RISC-V Cores
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
• Improving Cold-Start in Batteryless And Energy Harvesting Systems
• SmartRing
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core

This page is currently under development.