Difference between revisions of "Main Page"

Revision as of 15:33, 16 January 2014

Welcome to the IIS Projects page

In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.

• Object Detection and Tracking on the Edge
• Design of a Low Power Smart Sensing Multi-modal Vision Platform
• Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
• Energy Efficient AXI Interface to Serial Link Physical Layer
• Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
• User:Sarjmandpour
• Energy Efficient Serial Link
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
• BirdGuard
• ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
• Audio Visual Speech Separation and Recognition (1S/1M)
• Predict eye movement through brain activity
• Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
• Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
• Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
• Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
• Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
• Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
• Implementation of a Coherent Application-Class Multicore System (1-2S)
• Resource Partitioning of Caches
• Resource Partitioning of RPC DRAM
• Bandwidth Efficient NEureka
• Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
• Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
• Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
• Big Data Analytics Benchmarks for Ara
• Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
• Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
• Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
• Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
• Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
• All the flavours of FFT on MemPool (1-2S/B)
• AXI-based Network on Chip (NoC) system
• User:Cioflanc
• Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
• Enabling Efficient Systolic Execution on MemPool (M)
• Radiation Testing of a PULP ASIC
• Virtual Memory Ara
• Ultrasound image data recycler
• Runtime partitioning of L1 memory in Mempool (1-2S/B)
• GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
• Extended Verification for Ara
• On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
• Ultrasound based hand gesture recognition
• Development of statistics and contention monitoring unit for PULP
• Design of combined Ultrasound and PPG systems
• Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
• A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
• Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
• Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
• An Efficient Compiler Backend for Snitch (1S/B)
• Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
• Implementing Configurable Dual-Core Redundancy
• Running Rust on PULP
• Optimizing the Pipeline in our Floating Point Architectures (1S)
• PULP Freertos with LLVM
• Zephyr RTOS on PULP
• Integration Of A Smart Vision System
• Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
• Towards Formal Verification of the iDMA Engine (1-3S/B)
• Event-based navigation on autonomous nano-drones
• Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
• Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
• Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
• Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
• Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
• Improving datarate and efficiency of ultra low power wearable ultrasound
• A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
• Battery indifferent wearable Ultrasound
• Design of combined Ultrasound and Electromyography systems
• Wearable Ultrasound for Artery monitoring
• Ultrasound Doppler system development
• Exploring NAS spaces with C-BRED
• Bridging QuantLab with LPDNN
• Machine Learning for extracting Muscle features from Ultrasound raw data
• Improved Collision Avoidance for Nano-drones
• Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
• Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
• New RVV 1.0 Vector Instructions for Ara
• User:Prasadar
• Triple-Core PULPissimo
• Deep Learning-based Global Local Planner for Autonomous Nano-drones
• Ultra-wideband Concurrent Ranging
• Smart e-glasses for concealed recording of EEG signals
• Fast Accelerator Context Switch for PULP
• PULP’s CLIC extensions for fast interrupt handling
• Neural Architecture Search using Reinforcement Learning and Search Space Reduction
• Visualization of Neural Architecture Search Spaces
• Wireless EEG Acquisition and Processing
• Self Aware Epilepsy Monitoring
• Enhancing our DMA Engine with Fault Tolerance
• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
• Watchdog Timer for PULP
• Serverless Benchmarks on RISC-V (M)
• Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
• Designing a Power Management Unit for PULP SoCs
• SCMI Support for Power Controller Subsystem
• Streaming Integer Extensions for Snitch (M/1-2S)
• Implementing DSP Instructions in Banshee (1S)
• A Unified Compute Kernel Library for Snitch (1-2S)
• Non-blocking Algorithms in Real-Time Operating Systems
• User:Fischeti
• Adding Linux Support to our DMA Engine (1-2S/B)
• Counter-based Fast Power Estimation using FPGAs (M/1-3S)
• Integrating Hardware Accelerators into Snitch (1S)
• Flexfloat DL Training Framework
• CLIC for the CVA6
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
• Mixed-Precision Neural Networks for Brain-Computer Interface Applications
• Ultra low power wearable ultrasound probe
• Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
• Feature Extraction for Speech Recognition (1S)
• Probing the limits of fake-quantised neural networks
• Analog Compute-in-Memory Accelerator Interface and Integration
• Machine Learning for extracting Muscle features using Ultrasound 2
• EEG artifact detection with machine learning
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
• EEG artifact detection for epilepsy monitoring
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
• Fast Simulation of Manycore Systems (1S)
• User:Vladn
• Ternary Neural Networks for Face Recognition
• Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
• Evaluating SoA Post-Training Quantization Algorithms
• Hardware/software codesign neural decoding algorithm for “neural dust”
• Novel Metastability Mitigation Technique
• Automatic unplugging detection for Ultrasound probes
• Ultrasound Low power WiFi with IMX7
• Ultrasound signal processing acceleration with CUDA
• Compression of Ultrasound data on FPGA
• Ibex: Tightly-Coupled Accelerators and ISA Extensions
• Huawei Research
• Implementation of an AES Hardware Processing Engine (B/S)
• Securing Block Ciphers against SCA and SIFA
• Graph neural networks for epileptic seizure detection
• Online Learning of User Features (1S)
• Wearables in Fashion
• Efficient TNN Inference on PULP Systems
• Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
• Implementing A Low-Power Sensor Node Network
• LLVM and DaCe for Snitch (1-2S)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• Heroino: Design of the next CORE-V Microcontroller
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
• Transforming MemPool into a CGRA (M)
• Manycore System on FPGA (M/S/G)
• Bluetooth Low Energy receiver in 65nm CMOS
• RVfplib
• Efficient Synchronization of Manycore Systems (M/1S)
• Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• Short Range Radars For Biomedical Application
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Matheus Cavalcante
• Smart Patch For Heath Care And Rehabilitation
• Autonomus Drones With Novel Sensors And Ultra Wide Band
• Evaluating memory access pattern specializations in OoO, server-grade cores (M)
• Evaluating An Ultra low Power Vision Node
• Hypervisor Extension for Ariane (M)
• Mapping Networks on Reconfigurable Binary Engine Accelerator
• Biomedical Circuits, Systems, and Applications
• User:Thoriri
• User:Georg
• Probabilistic training algorithms for quantized neural networks
• Exploring schedules for incremental and annealing quantization algorithms
• User:Susman
• ASIC Development of 5G-NR LDPC Decoder
• VLSI Implementation of a 5G Ciphering Accelerator
• Machine Learning on Ultrasound Images
• Low Latency Brain-Machine Interfaces
• IP-Based SoC Generation and Configuration (1-3S/B)
• Efficient TNN compression
• ISA extensions in the Snitch Processor for Signal Processing (M)
• MemPool on HERO (1S)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• Multi issue OoO Ariane Backend (M)
• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• PREM Runtime Scheduling Policies
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• User:Mmaxim
• User:Scheremo
• Event-Driven Vision on an embedded platform
• Smart Meters
• User:Lbertaccini
• Time Gain Compensation for Ultrasound Imaging
• Minimum Variance Beamforming for Wearable Ultrasound Probes

This page is currently under development.