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Welcome to IIS-Projects
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Institute Organization
The IIS Consists of 4 main research groups
- Analog and Mixed Signal Design
- Analog and Mixed Signal Interfaces
- Digital Circuits and Systems
- Nano-TCAD
Analog and Mixed Signal Design Group (Prof. Huang)
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Analog and Mixed Signal Interfaces Group (Prof. Jang)
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Digital Circuits and Systems Group (Prof. Benini)
- Computer Architecture
- Acceleration and Transprecision
- Heterogeneous Acceleration Systems
- Event-Driven Computing
- Predictable Execution
- Low Power Embedded Systems and Wireless Sensors Networks
- Embedded Artificial Intelligence:Systems And Applications
- Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
- Transient Computing
- RF SoCs for the Internet of Things
- Energy Efficient Autonomous UAVs
- Biomedical System on Chips
- Digital Medical Ultrasound Imaging
- Cryptographic Hardware
- Deep Learning Acceleration
- Human Intranet
Nano-TCAD Group (Prof. Luisier)
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Charge and heat transport through graphene nanoribbon based devices
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Integrated silicon photonic structures-Lumiphase
- Characterization techniques for silicon photonics-Lumiphase
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Phase-change memory devices for emerging computing paradigms
- Finite element modeling of electrochemical random access memory
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Quantum transport in 2D heterostructures
- Development of an efficient algorithm for quantum transport codes
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Redox Processes in CBRAM
Collaborations with other groups/departments
Selected Projects in Progress
For a complete list, see Projects in Progress.
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Low Precision Ara for ML
- Virtual Memory Ara
- New RVV 1.0 Vector Instructions for Ara
Selected Completed Projects
For a complete list, see Completed Projects.
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Resource Partitioning of Caches
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
Selected Research Projects
For a complete list, see Research Projects.
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Resource Partitioning of Caches
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
Links to Other IIS Webpages
- http://www.iis.ee.ethz.ch
- Integrated Systems Laboratory Main homepage
- http://www.nano-tcad.ethz.ch
- Nano-TCAD group homepage
- http://www.dz.ee.ethz.ch
- Microelectronics Design Center
- http://asic.ethz.ch/cg
- The IIS-ASIC Chip Gallery
- http://eda.ee.ethz.ch
- EDA Wiki (ETH Zurich internal access only!)
