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Revision as of 12:43, 9 February 2015
Welcome to IIS-Projects
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Institute Organization
The IIS Consists of 4 main research groups
- Analog and Mixed Signal Design
- IC and Systems, Design and Test
- Nano Electronics and Nano Photonics
- Nano-TCAD
Available Hot Student Projects
For a complete list, see Available Projects.
Analog Design
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Digital Design
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Federated Continual Learning on Nano-Drone Swarms
- Extreme-Edge Experience Replay for Keyword Spotting
Nano Electronics
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
Nano-TCAD
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Charge and heat transport through graphene nanoribbon based devices
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- Every individual on the planet should have a real chance to obtain personalized medical therapy
Selected Projects in Progress
For a complete list, see Projects in Progress.
- ASR-Waveformer
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Fault-Tolerant Floating-Point Units (M)
Selected Completed Projects
For a complete list, see Completed Projects.
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Exploring NAS spaces with C-BRED
- Bandwidth Efficient NEureka
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
Selected Research Projects
For a complete list, see Research Projects.
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Exploring NAS spaces with C-BRED
- Bandwidth Efficient NEureka
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
Links to Other IIS Webpages
- http://www.iis.ee.ethz.ch
- Integrated Systems Laboratory Main homepage
- http://lne.ee.ethz.ch
- Laboratory for Nanoelectronics homepage
- http://www.nano-tcad.ethz.ch
- Nano-TCAD group homepage
- http://www.dz.ee.ethz.ch
- Microelectronics Design Center
- http://asic.ethz.ch/cg
- The IIS-ASIC Chip Gallery
- http://eda.ee.ethz.ch
- EDA Wiki (ETH Zurich internal access only!)