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In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Available Projects
Hot Projects
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Federated Continual Learning on Nano-Drone Swarms
- Neural Recording Interface and Spike Sorting Algorithm
- Extreme-Edge Experience Replay for Keyword Spotting
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- GPT on the edge
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Design of Streaming Data Platform for High-Speed ADC Data
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Realtime Gaze Tracking on Siracusa
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Charge and heat transport through graphene nanoribbon based devices
- Energy Efficient Serial Link
- Audio Visual Speech Separation and Recognition (1S/1M)
- Predict eye movement through brain activity
- Design of low mismatch DAC used for VAD
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Integration Of A Smart Vision System
- Event-based navigation on autonomous nano-drones
- Development of an implantable Force sensor for orthopedic applications
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Improved Collision Avoidance for Nano-drones
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Fast Accelerator Context Switch for PULP
- Visualization of Neural Architecture Search Spaces
- Self Aware Epilepsy Monitoring
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Non-blocking Algorithms in Real-Time Operating Systems
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Fast Simulation of Manycore Systems (1S)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Integrated silicon photonic structures-Lumiphase
- Characterization techniques for silicon photonics-Lumiphase
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Huawei Research
- IBM Research
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- BCI-controlled Drone
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Phase-change memory devices for emerging computing paradigms
- Finite element modeling of electrochemical random access memory
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Quantum transport in 2D heterostructures
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Design and implementation of the front-end for a portable ionizing radiation detector
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Real-Time Implementation of Quantum State Identification using an FPGA
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Towards Online Training of CNNs: Hebbian-Based Deep Learning
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Development of a syringe label reader for the neurocritical care unit
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- PVT Dynamic Adaptation in PULPv3
- Linux Driver for fine-grain and low overhead access to on-chip performance counters
- Open Power-On Chip Controller Study and Integration
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Using Motion Sensors to Support Indoor Localization
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Development of an efficient algorithm for quantum transport codes
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Redox Processes in CBRAM
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
Digital Design
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Federated Continual Learning on Nano-Drone Swarms
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extreme-Edge Experience Replay for Keyword Spotting
- Low Precision Ara for ML
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- FPGA mapping of RPC DRAM
- GPT on the edge
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Modeling FlooNoC in GVSoC (S/M)
- Advanced Data Movers for Modern Neural Networks
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Realtime Gaze Tracking on Siracusa
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- BirdGuard
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Predict eye movement through brain activity
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Resource Partitioning of RPC DRAM
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ultrasound image data recycler
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Extended Verification for Ara
- Design of combined Ultrasound and PPG systems
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- PULP Freertos with LLVM
- Integration Of A Smart Vision System
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Event-based navigation on autonomous nano-drones
- Improving datarate and efficiency of ultra low power wearable ultrasound
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Battery indifferent wearable Ultrasound
- Wearable Ultrasound for Artery monitoring
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Improved Collision Avoidance for Nano-drones
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Ultra-wideband Concurrent Ranging
- Enhancing our DMA Engine with Fault Tolerance
- Fast Accelerator Context Switch for PULP
- Visualization of Neural Architecture Search Spaces
- Self Aware Epilepsy Monitoring
- Serverless Benchmarks on RISC-V (M)
- Non-blocking Algorithms in Real-Time Operating Systems
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Fast Simulation of Manycore Systems (1S)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Automatic unplugging detection for Ultrasound probes
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Huawei Research
- Securing Block Ciphers against SCA and SIFA
- RVfplib
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Short Range Radars For Biomedical Application
- Smart Patch For Heath Care And Rehabilitation
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Machine Learning on Ultrasound Images
- IP-Based SoC Generation and Configuration (1-3S/B)
- Efficient Search Design for Hyperdimensional Computing
- PREM Runtime Scheduling Policies
- IBM Research
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- BCI-controlled Drone
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Accurate deep learning inference using computational memory
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Extending the RISCV backend of LLVM to support PULP Extensions
- Compiler Profiling and Optimizing
- PREM Intervals and Loop Tiling
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- PREM on PULP
- Edge Computing for Long-Term Wearable Biomedical Systems
- AMZ Driverless Competition Embedded Systems Projects
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Wireless Sensing With Long Range Comminication (LoRa)
- Indoor Smart Tracking of Hospital instrumentation
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- Physics is looking for PULP
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- An Industrial-grade Bluetooth LE Mesh Network Solution
- BLISS - Battery-Less Identification System for Security
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Zero Power Touch Sensor and Reciever For Body Communication
- Wake Up Radio For Energy Efficient Communication System and IC Design
- A Wireless Sensor Network for HPC monitoring
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Power Geolocalization And Indoor Localization
- Real-Time Implementation of Quantum State Identification using an FPGA
- Neural Networks Framwork for Embedded Plattforms
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Single-Bit-Synapse Spiking Neural System-on-Chip
- OpenRISC SoC for Sensor Applications
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- PVT Dynamic Adaptation in PULPv3
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Towards The Integration of E-skin into Prosthetic Devices
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Towards Self Sustainable UAVs
- Using Motion Sensors to Support Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Bateryless Heart Rate Monitoring
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Kinetic Energy Harvesting For Autonomous Smart Watches
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomous Smart Watches: Hardware and Software Desing
- A Wireless Sensor Network for a Smart LED Lighting control
- Compressed Sensing vs JPEG
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Real-Time Pedestrian Detection For Privacy Enhancement
- Thermal Control of Mobile Devices
- Android reliability governor
- Infrared Wake Up Radio
- Ambient RF Energy harvesting for Wireless Sensor Network
- Hardware Support for IDE in Multicore Environment
- Audio DAC Conversion Jitter Measurement System
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Variability Tolerant Ultra Low Power Cluster
All Projects
Digital Design
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Federated Continual Learning on Nano-Drone Swarms
- ASR-Waveformer
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extreme-Edge Experience Replay for Keyword Spotting
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Writing a Hero runtime for EPAC (1-3S/B)
- FPGA mapping of RPC DRAM
- GPT on the edge
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Modeling FlooNoC in GVSoC (S/M)
- Advanced Data Movers for Modern Neural Networks
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Fault-Tolerant Floating-Point Units (M)
- Efficient collective communications in FlooNoC (1M)
- Low Precision Ara for ML
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- Streaming Layer Normalization in ITA (M/1-2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Physical Implementation of ITA (2S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Realtime Gaze Tracking on Siracusa
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound-EMG combined hand gesture recognition
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- RedCap-5G for IOT application on prototype taped-out silicon
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Transformer Deployment on Heterogeneous Many-Core Systems
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- Implementation of a Cache Reliability Mechanism (1S/M)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- On - Device Continual Learning for Seizure Detection on GAP9
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- Real-time Linux on RISC-V
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- On-Board Software for PULP on a Satellite
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- User:Sarjmandpour
- Energy Efficient Serial Link
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- BirdGuard
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Predict eye movement through brain activity
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Resource Partitioning of Caches
- Resource Partitioning of RPC DRAM
- Bandwidth Efficient NEureka
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Big Data Analytics Benchmarks for Ara
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- AXI-based Network on Chip (NoC) system
- User:Cioflanc
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Enabling Efficient Systolic Execution on MemPool (M)
- Radiation Testing of a PULP ASIC
- Virtual Memory Ara
- Ultrasound image data recycler
- Runtime partitioning of L1 memory in Mempool (M)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Extended Verification for Ara
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ultrasound based hand gesture recognition
- Development of statistics and contention monitoring unit for PULP
- Design of combined Ultrasound and PPG systems
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Implementing Configurable Dual-Core Redundancy
- Running Rust on PULP
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- PULP Freertos with LLVM
- Zephyr RTOS on PULP
- Integration Of A Smart Vision System
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Event-based navigation on autonomous nano-drones
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Improving datarate and efficiency of ultra low power wearable ultrasound
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Battery indifferent wearable Ultrasound
- Design of combined Ultrasound and Electromyography systems
- Wearable Ultrasound for Artery monitoring
- Ultrasound Doppler system development
- Exploring NAS spaces with C-BRED
- Bridging QuantLab with LPDNN
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Improved Collision Avoidance for Nano-drones
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- New RVV 1.0 Vector Instructions for Ara
- User:Prasadar
- Triple-Core PULPissimo
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Ultra-wideband Concurrent Ranging
- Smart e-glasses for concealed recording of EEG signals
- Fast Accelerator Context Switch for PULP
- PULP’s CLIC extensions for fast interrupt handling
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Visualization of Neural Architecture Search Spaces
- Wireless EEG Acquisition and Processing
- Self Aware Epilepsy Monitoring
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Watchdog Timer for PULP
- Serverless Benchmarks on RISC-V (M)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Designing a Power Management Unit for PULP SoCs
- SCMI Support for Power Controller Subsystem
- Streaming Integer Extensions for Snitch (M/1-2S)
- Implementing DSP Instructions in Banshee (1S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- Non-blocking Algorithms in Real-Time Operating Systems
- User:Fischeti
- Adding Linux Support to our DMA Engine (1-2S/B)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Integrating Hardware Accelerators into Snitch (1S)
- Flexfloat DL Training Framework
- CLIC for the CVA6
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Ultra low power wearable ultrasound probe
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Probing the limits of fake-quantised neural networks
- Analog Compute-in-Memory Accelerator Interface and Integration
- Machine Learning for extracting Muscle features using Ultrasound 2
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
