Manycore System on FPGA (M/S/G)
- 1 Overview
- 2 Introduction
- 3 Project Description
- 4 Project Realization
- 5 Deliverables
- 6 References
- 7 References
- Student: Enis Mustafa
- Type: Bachelor/Semester/Master Thesis
- Professor: Prof. Dr. L. Benini
- RTL design
- FPGA design
- VLSI I (recommended)
- Experience with C
In a quest for high-performance computing systems, few architectural models retain the flexibility of many-core systems. Those systems integrate many small cores (hundreds, thousands) that work independently to execute highly-parallelizable algorithms.
At ETH, we are developing our own many-core system called MemPool . It boasts 256 lightweight 32-bit Snitch cores developed at ETH . They implement the RISC-V instruction set architecture (ISA), a modular and open ISA . Despite its size, MemPool manages to give all 256 cores low-latency access to the shared L1 memory, with a maximum latency of only five cycles. Therefore, all cores can efficiently communicate, making MemPool suitable for various workloads and easy to program.
For development purposes, we recently implemented a small version of MemPool on an FPGA. Specifically, we have a version of MemPool with 16 Snitch cores working on a Zynq® UltraScale+™ MPSoC. This chip features an ARM host core, which we use as a host to our many-core accelerator system.
While this prototype is working well, there are a few features we would like to add or improve. The goal of a MemPool based FPGA project would be to work on one or multiple of the following aspects.
- Our system currently uses 57% of the FPGA's resources with 16 Snitch cores. However, we want to get to 32. A potential project would be to optimize the RTL for the FPGA to make it more area efficient and squeeze 32 cores onto a single FPGA board.
- A missing feature we have at the moment is debugging capability. For example, we lack the ability to print from the MemPool system. A thesis involving RTL and software design could implement this feature.
- We want to use the FPGA prototype to benchmark applications. But currently, we can only measure the number of cycles and instructions when running benchmarks on MemPool. Adding hardware performance counters and host software to read this would be very beneficial.
- We have a simple host software that communicates with MemPool and allows us to offload tasks to MemPool. However, there is currently very little communication, and most of it is done through polling. Adding a device driver for MemPool would make offloading tasks easier and could cut out much of the overhead.
If a project along these directions interests you, or you have ideas of how you could extend MemPool on the FPGA, contact us, and we design a project that fits your background and interests.
Weekly meetings will be held between the student and the assistants. The exact time and location of these meetings will be determined within the first week of the project in order to fit the student’s and the assistants’ schedule. These meetings will be used to evaluate the status and progress of the project. Besides these regular meetings, additional meetings can be organized to address urgent issues as well.
Master Thesis: The student is required to write a weekly report at the end of each week and to send it to his advisors by email. The idea of the weekly report is to briefly summarize the work, progress and any findings made during the week, plan the actions for the next week, and discuss open questions and points. The weekly report is also an important means for the student to get a goal-oriented attitude to work.
Semester Thesis: The student is advised, but not required, to write a weekly report at the end of each week and to send it to his advisors. The idea of the weekly report is to briefly summarize the work, progress and any findings made during the week, plan the actions for the next week, and bring up open questions and points. The weekly report is also an important means for the student to get a goal-oriented attitude to work.
HDL Code Style
Adapting a consistent code style is one of the most important steps in order to make your code easy to understand. If signals, processes, and modules are always named consistently, any inconsistency can be detected more easily. Moreover, if a design group shares the same naming and formatting conventions, all members immediately feel at home with each other’s code. At IIS, we use lowRISC’s style guide for SystemVerilog HDL: https://github.com/lowRISC/style-guides/.
Software Code Style
We generally suggest that you use style guides or code formatters provided by the language’s developers or community. For example, we recommend LLVM’s or Google’s code styles with
clang-format for C/C++, PEP-8 and
pylint for Python, and the official style guide with
rustfmt for Rust.
Even in the context of a student project, keeping a precise history of changes is essential to a maintainable codebase. You may also need to collaborate with others, adopt their changes to existing code, or work on different versions of your code concurrently. For all of these purposes, we heavily use Git as a version control system at IIS. If you have no previous experience with Git, we strongly advise you to familiarize yourself with the basic Git workflow before you start your project.
Documentation is an important and often overlooked aspect of engineering. A final report has to be completed within this project.
The common language of engineering is de facto English. Therefore, the final report of the work is preferred to be written in English.
Any form of word processing software is allowed for writing the reports, nevertheless, the use of LaTeX with Inkscape or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
If you write the report in LaTeX, we offer an instructive, ready-to-use template, which can be forked from the Git repository at https://iis-git.ee.ethz.ch/akurth/iisreport.
The final report has to be presented at the end of the project and a digital copy needs to be handed in and remain property of the IIS. Note that this task description is part of your report and has to be attached to your final report.
There will be a presentation 15/20 min presentation and 5 min Q&A at the end of this project in order to present your results to a wider audience. The exact date will be determined towards the end of the work.
In order to complete the project successfully, the following deliverables have to be submitted at the end of the work:
- Final report incl. presentation slides
- Source code and documentation for all developed software and hardware
- Testsuites (software) and testbenches (hardware)
- Synthesis and implementation scripts, results, and reports
 M. Cavalcante, S. Riedel, A. Pullini, and L. Benini, “MemPool: A shared-L1 memory many-core cluster with a low-latency interconnect.” 2020.
 F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads.” 2020.
 A. Waterman et al., “The RISC-V instruction set manual.” 2014.