Personal tools

Difference between revisions of "Marco Bertuletti"

From iis-projects

Jump to: navigation, search
(Created page with "== Marco Bertuletti == I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I a...")
 
 
(36 intermediate revisions by 2 users not shown)
Line 1: Line 1:
== Marco Bertuletti ==
+
[[File:PULP_ID.jpeg|200px|thumb|right]]
 
 
  
 
I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
 
I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
  
== Interests ==
+
==Research interests==
  
 
My main research interests are:
 
My main research interests are:
Line 10: Line 9:
 
* Parallel Programming
 
* Parallel Programming
 
* Manycore systems
 
* Manycore systems
 +
* New radio baseband processing
 +
 +
I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory.
 +
 +
==Contact==
  
==Contact Information==
 
 
* '''Office''': ETZ J71.2  
 
* '''Office''': ETZ J71.2  
 
* '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch]
 
* '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch]
 
* '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)]
 
* '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)]
 +
 +
==Projects==
 +
 +
===Available Projects===
 +
<DynamicPageList>
 +
category = Available
 +
category = Mbertuletti
 +
suppresserrors=true
 +
ordermethod=sortkey
 +
order=ascending
 +
</DynamicPageList>

Latest revision as of 10:22, 10 August 2022

PULP ID.jpeg

I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.

Research interests

My main research interests are:

  • Computer and System Architecture
  • Parallel Programming
  • Manycore systems
  • New radio baseband processing

I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory.

Contact

Projects

Available Projects