Difference between revisions of "Marco Bertuletti"
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| − | [[File:PULP_ID.jpeg| | + | [[File:PULP_ID.jpeg||140px|thumb|right]] |
| − | + | I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. | |
| − | + | Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini. | |
| + | |||
| + | ==Research interests== | ||
My main research interests are: | My main research interests are: | ||
| − | |||
* Parallel Programming | * Parallel Programming | ||
* Manycore systems | * Manycore systems | ||
| + | * New radio baseband processing | ||
| + | |||
| + | I work on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory. If you are interested in one of my projects or you would like to discuss about my research feel free to drop me an e-mail or to pass by my office! | ||
==Contact== | ==Contact== | ||
| − | * '''Office''': ETZ | + | |
| + | * '''Office''': ETZ J69.2 | ||
* '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch] | * '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch] | ||
* '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)] | * '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)] | ||
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ordermethod=sortkey | ordermethod=sortkey | ||
order=ascending | order=ascending | ||
| + | </DynamicPageList> | ||
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| + | ===Projects In Progress=== | ||
| + | <DynamicPageList> | ||
| + | category = In progress | ||
| + | category = Mbertuletti | ||
</DynamicPageList> | </DynamicPageList> | ||
Latest revision as of 17:20, 9 November 2022
I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively.
Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
Research interests
My main research interests are:
- Parallel Programming
- Manycore systems
- New radio baseband processing
I work on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory. If you are interested in one of my projects or you would like to discuss about my research feel free to drop me an e-mail or to pass by my office!
Contact
- Office: ETZ J69.2
- e-mail: mbertuletti@iis.ee.ethz.ch
- www: Marco Bertuletti (ETH page)
Projects
Available Projects
- All the flavours of FFT on MemPool (1-2S/B)
- RedCap-5G for IOT application on prototype taped-out silicon
- Runtime partitioning of L1 memory in Mempool (1-2S/B)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
