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Difference between revisions of "Marco Bertuletti"

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I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
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I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively.  
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Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
  
 
==Research interests==
 
==Research interests==
  
 
My main research interests are:
 
My main research interests are:
* Computer and System Architecture
 
 
* Parallel Programming
 
* Parallel Programming
 
* Manycore systems
 
* Manycore systems
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* New radio baseband processing
  
I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures, have respectively 256 and 1024 cores, sharing a large L1 data memory.
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I work on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory. If you are interested in one of my projects or you would like to discuss about my research feel free to drop me an e-mail or to pass by my office!
  
 
==Contact==
 
==Contact==
  
* '''Office''': ETZ J71.2  
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* '''Office''': ETZ J69.2  
 
* '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch]
 
* '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch]
 
* '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)]
 
* '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)]
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===Projects In Progress===
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category = In progress
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category = Mbertuletti
 
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Latest revision as of 16:20, 9 November 2022

Mbertuletti picture.jpeg

I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively.

Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.

Research interests

My main research interests are:

  • Parallel Programming
  • Manycore systems
  • New radio baseband processing

I work on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory. If you are interested in one of my projects or you would like to discuss about my research feel free to drop me an e-mail or to pass by my office!

Contact

Projects

Available Projects


Projects In Progress