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Difference between revisions of "Marco Bertuletti"

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[[File:PULP_ID.jpeg||140px|thumb|right]]
 
[[File:PULP_ID.jpeg||140px|thumb|right]]
  
I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
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I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively.  
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Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
  
 
==Research interests==
 
==Research interests==
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* New radio baseband processing
 
* New radio baseband processing
  
I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory. If you are interested in one of my projects or you would like to discuss about my research feel free to drop me an e-mail or to pass by my office!
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I work on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory. If you are interested in one of my projects or you would like to discuss about my research feel free to drop me an e-mail or to pass by my office!
  
 
==Contact==
 
==Contact==
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<DynamicPageList>
 
category = Available
 
category = Available
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category = Mbertuletti
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suppresserrors=true
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order=ascending
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===Reserved Projects===
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<DynamicPageList>
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category = Reserved
 
category = Mbertuletti
 
category = Mbertuletti
 
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<DynamicPageList>
 
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category = In progress
 
category = In progress
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category = Mbertuletti
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===Projects Completed===
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<DynamicPageList>
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category = Completed
 
category = Mbertuletti
 
category = Mbertuletti
 
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Latest revision as of 10:29, 23 December 2023

Mbertuletti picture.jpeg

I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively.

Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.

Research interests

My main research interests are:

  • Parallel Programming
  • Manycore systems
  • New radio baseband processing

I work on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory. If you are interested in one of my projects or you would like to discuss about my research feel free to drop me an e-mail or to pass by my office!

Contact

Projects

Available Projects


Reserved Projects


Projects In Progress


Projects Completed