Difference between revisions of "Marco Bertuletti"
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Mbertuletti (talk | contribs) (Created page with "== Marco Bertuletti == I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I a...") |
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* '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch] | * '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch] | ||
* '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)] | * '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.MzAyNTU4.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Marco Bertuletti (ETH page)] | ||
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| + | ==Projects== | ||
| + | |||
| + | ===Available Projects=== | ||
| + | <DynamicPageList> | ||
| + | category = Available | ||
| + | category = Mbertuletti | ||
| + | suppresserrors=true | ||
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| + | order=ascending | ||
| + | </DynamicPageList> | ||
| + | |||
| + | ===Reserved Projects=== | ||
| + | <DynamicPageList> | ||
| + | category = Reserved | ||
| + | category = Mbertuletti | ||
| + | suppresserrors=true | ||
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| + | order=ascending | ||
| + | </DynamicPageList> | ||
| + | |||
| + | ===Projects In Progress=== | ||
| + | <DynamicPageList> | ||
| + | category = In progress | ||
| + | category = Mbertuletti | ||
| + | suppresserrors=true | ||
| + | ordermethod=sortkey | ||
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| + | </DynamicPageList> | ||
| + | |||
| + | ===Completed Projects=== | ||
| + | <DynamicPageList> | ||
| + | category = Completed | ||
| + | category = Mbertuletti | ||
| + | suppresserrors=true | ||
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| + | </DynamicPageList> | ||
Revision as of 07:59, 9 August 2022
Contents
Marco Bertuletti
I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
Interests
My main research interests are:
- Computer and System Architecture
- Parallel Programming
- Manycore systems
Contact Information
- Office: ETZ J71.2
- e-mail: mbertuletti@iis.ee.ethz.ch
- www: Marco Bertuletti (ETH page)
Projects
Available Projects
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- All the flavours of FFT on MemPool (1-2S/B)
- RedCap-5G for IOT application on prototype taped-out silicon
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
Reserved Projects
Projects In Progress
- Runtime partitioning of L1 memory in Mempool (M)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
