I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
My main research interests are:
- Computer and System Architecture
- Parallel Programming
- Manycore systems
I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures, have respectively 256 and 1024 cores, sharing a large L1 data memory.
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- All the flavours of FFT on MemPool (1-2S/B)
- RedCap-5G for IOT application on prototype taped-out silicon
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)