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Difference between revisions of "Marco Bertuletti"

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[[File:PULP_ID.jpeg|200px|thumb|right]]
 
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==About me==
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I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
  
I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
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==Research interests==
  
 
My main research interests are:
 
My main research interests are:
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* Parallel Programming
 
* Parallel Programming
 
* Manycore systems
 
* Manycore systems
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* New radio baseband processing
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I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory.
  
 
==Contact==
 
==Contact==

Revision as of 09:22, 10 August 2022

Mbertuletti picture.jpeg

I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.

Research interests

My main research interests are:

  • Computer and System Architecture
  • Parallel Programming
  • Manycore systems
  • New radio baseband processing

I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory.

Contact

Projects

Available Projects