Difference between revisions of "Marco Bertuletti"
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Revision as of 16:24, 12 October 2022
I completed my B.Sc. and M.Sc. in Electronics Engineering at Politecnico di Milano in July 2019 and December 2021, respectively. Since March 2022, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
Research interests
My main research interests are:
- Parallel Programming
- Manycore systems
- New radio baseband processing
I work with Huawei Sweden on the implementation of 5G physical uplink shared channel on Mempool and Terapool. These two IIS born manycore architectures have respectively 256 and 1024 cores, sharing a large L1 data memory.
Contact
- Office: ETZ J71.2
- e-mail: mbertuletti@iis.ee.ethz.ch
- www: Marco Bertuletti (ETH page)
Projects
Available Projects
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- All the flavours of FFT on MemPool (1-2S/B)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
