Difference between revisions of "Michael Rogenmoser"

Revision as of 08:35, 9 August 2022

I finished my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2020 and 2021, respectively. Since summer 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.

My main research areas are:

• Fault Tolerant architectures for Space
• Multicore processors
• Reliability in SoCs

If you are interested any projects, or would like to chat about space, feel free to send me an email or drop by my office.

Contact

• e-mail: michaero@iis.ee.ethz.ch
• phone: +41 44 632 54 33
• office: ETZ J69.2
• github: micprog

Projects

Available Projects

• Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
• Enhancing our DMA Engine with Fault Tolerance
• Scan Chain Fault Injection in a PULP SoC (1S)
• Towards Formal Verification of the iDMA Engine (1-3S/B)

Reserved Projects

• Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)

Projects In Progress

• Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
• Fault-Tolerant Floating-Point Units (M)
• Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
• Implementation of a Cache Reliability Mechanism (1S/M)
• On-Board Software for PULP on a Satellite
• A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
• Radiation Testing of a PULP ASIC

Completed Projects

• Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
• Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
• Implementing Configurable Dual-Core Redundancy
• Running Rust on PULP
• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
• Adding Linux Support to our DMA Engine (1-2S/B)
• Triple-Core PULPissimo
• Watchdog Timer for PULP
• Hypervisor Extension for Ariane (M)