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Difference between revisions of "Minimal Cost RISC-V core"

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  [[Category:Digital]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]]
  [[Category:Digital]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]

Revision as of 15:29, 15 March 2016

Mini riscv.png

Short Description

RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. Our core currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also added several instruction set extensions. A micro-controller on the other hand, does not need the full support of all the extensions. When minimal hardware costs, and ultra low power consumption is the most important requirement of a system, a micro-controller with support of only basic instructions is enough. In this project you are going to design a micro-architecture which minimizes the area footprint and power consumption in order to outperform an ARM Cortex M0.

Status: Available

Supervisors: Michael Gautschi


Interest in Computer Architectures (RISC architectures)
VHDL/System Verilog knowledge
Programming in C


25% Theory
50% ASIC Design
25% EDA tools


Luca Benini

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Detailed Task Description


Practical Details