http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&feed=atom&action=history
Minimal Cost RISC-V core - Revision history
2024-03-29T11:53:48Z
Revision history for this page on the wiki
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http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=4727&oldid=prev
Kgf at 15:24, 21 August 2019
2019-08-21T15:24:40Z
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Kgf
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2571&oldid=prev
Gautschi at 09:27, 23 December 2016
2016-12-23T09:27:31Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:27, 23 December 2016</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>===Status: <del class="diffchange diffchange-inline">Available </del>===</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>===Status: <ins class="diffchange diffchange-inline">Ongoing </ins>===</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Supervisors: [[:User:Pullinia|Antonio Pullini]]</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Supervisors: [[:User:Pullinia|Antonio Pullini]]</div></td></tr>
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Gautschi
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2570&oldid=prev
Gautschi at 09:27, 23 December 2016
2016-12-23T09:27:16Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:27, 23 December 2016</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>: Supervisors: [[:User:<del class="diffchange diffchange-inline">pullini</del>|Antonio Pullini]]</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>: Supervisors: [[:User:<ins class="diffchange diffchange-inline">Pullinia</ins>|Antonio Pullini]]</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Prerequisites===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Prerequisites===</div></td></tr>
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Gautschi
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2569&oldid=prev
Gautschi at 09:26, 23 December 2016
2016-12-23T09:26:42Z
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>: Supervisors: [[:User:<del class="diffchange diffchange-inline">gautschi</del>|<del class="diffchange diffchange-inline">Michael Gautschi</del>]]</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>: Supervisors: [[:User:<ins class="diffchange diffchange-inline">pullini</ins>|<ins class="diffchange diffchange-inline">Antonio Pullini</ins>]]</div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Prerequisites===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Prerequisites===</div></td></tr>
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Gautschi
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2129&oldid=prev
Gautschi at 16:45, 14 April 2016
2016-04-14T16:45:02Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 16:45, 14 April 2016</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l3" >Line 3:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. Our core currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also added several instruction set extensions.</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. Our core currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also added several instruction set extensions.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>A simple micro-controller on the other hand, does not need the full support of all the extensions. Instead minimal hardware costs and ultra low power consumption are the most important requirements of such system. For this purpose a processor which only supports the basic instructions is enough and <del class="diffchange diffchange-inline">is thus able </del>to <del class="diffchange diffchange-inline">achieve a higher energy-efficiency than a </del>signal-processing <del class="diffchange diffchange-inline">optimized core</del>.</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>A simple micro-controller on the other hand, does not need the full support of all the extensions. Instead minimal hardware costs and ultra low power consumption are the most important requirements of such <ins class="diffchange diffchange-inline">a </ins>system. For this purpose a processor which only supports the basic instructions is enough<ins class="diffchange diffchange-inline">. A very simple 2-3stage pipeline </ins>and <ins class="diffchange diffchange-inline">minimal support for the number of registers can further decrease the power consumption which allows </ins>to <ins class="diffchange diffchange-inline">outperform other cores which are optimized for </ins>signal-processing <ins class="diffchange diffchange-inline">tasks</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>In this project you are going to design a CPU micro-architecture which minimizes the area footprint and power consumption in order to outperform an ARM Cortex M0. The focus lies on reducing power consumption which is the most important metric. To achieve this every aspect of the design must be done with low power and minimum area in mind.</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>In this project you are going to design a CPU micro-architecture which minimizes the area footprint and power consumption in order to outperform an ARM Cortex M0 <ins class="diffchange diffchange-inline">and other low power cores</ins>. The focus lies on reducing power consumption which is the most important metric. To achieve this every aspect of the design must be done with low power and minimum area in mind.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: 50% ASIC Design</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: 50% ASIC Design</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>: 25% <del class="diffchange diffchange-inline">EDA tools</del></div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>: 25% <ins class="diffchange diffchange-inline">Verification</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Professor===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Professor===</div></td></tr>
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Gautschi
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2006&oldid=prev
Atraber at 14:35, 15 March 2016
2016-03-15T14:35:52Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 14:35, 15 March 2016</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l1" >Line 1:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>[[File:mini_riscv.png|1600px|right|thumb]]</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>[[File:mini_riscv.png|1600px|right|thumb]]</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Short Description==</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>==Short Description==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. Our core currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also added several instruction set extensions. A micro-controller on the other hand, does not need the full support of all the extensions. <del class="diffchange diffchange-inline">When </del>minimal hardware costs<del class="diffchange diffchange-inline">, </del>and ultra low power consumption <del class="diffchange diffchange-inline">is </del>the most important <del class="diffchange diffchange-inline">requirement </del>of <del class="diffchange diffchange-inline">a </del>system<del class="diffchange diffchange-inline">, </del>a <del class="diffchange diffchange-inline">micro-controller with support of </del>only basic instructions is enough.</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. Our core currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also added several instruction set extensions.</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>In this project you are going to design a micro-architecture which minimizes the area footprint and power consumption in order to outperform an ARM Cortex M0.</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div> </div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>A <ins class="diffchange diffchange-inline">simple </ins>micro-controller on the other hand, does not need the full support of all the extensions. <ins class="diffchange diffchange-inline">Instead </ins>minimal hardware costs and ultra low power consumption <ins class="diffchange diffchange-inline">are </ins>the most important <ins class="diffchange diffchange-inline">requirements </ins>of <ins class="diffchange diffchange-inline">such </ins>system<ins class="diffchange diffchange-inline">. For this purpose </ins>a <ins class="diffchange diffchange-inline">processor which </ins>only <ins class="diffchange diffchange-inline">supports the </ins>basic instructions is enough <ins class="diffchange diffchange-inline">and is thus able to achieve a higher energy-efficiency than a signal-processing optimized core</ins>.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div> </div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>In this project you are going to design a <ins class="diffchange diffchange-inline">CPU </ins>micro-architecture which minimizes the area footprint and power consumption in order to outperform an ARM Cortex M0<ins class="diffchange diffchange-inline">. The focus lies on reducing power consumption which is the most important metric. To achieve this every aspect of the design must be done with low power and minimum area in mind</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
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Atraber
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2004&oldid=prev
Atraber at 14:29, 15 March 2016
2016-03-15T14:29:47Z
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>  [[Category:Digital]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]]</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>  [[Category:Digital]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP<ins class="diffchange diffchange-inline">]] [[Category:Processor</ins>]]</div></td></tr>
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Atraber
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2003&oldid=prev
Gautschi at 14:20, 15 March 2016
2016-03-15T14:20:30Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 14:20, 15 March 2016</td>
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<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>  [[Category:Digital]] [[Category:<del class="diffchange diffchange-inline">Master </del>Thesis]] [[Category:Available]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]]</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>  [[Category:Digital]] [[Category:<ins class="diffchange diffchange-inline">Semester </ins>Thesis]] [[Category:Available]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]]</div></td></tr>
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Gautschi
http://iis-projects.ee.ethz.ch/index.php?title=Minimal_Cost_RISC-V_core&diff=2001&oldid=prev
Gautschi: Created page with "thumb ==Short Description== RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture..."
2016-03-15T14:18:22Z
<p>Created page with "<a href="/index.php?title=File:Mini_riscv.png" title="File:Mini riscv.png">1600px|right|thumb</a> ==Short Description== RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture..."</p>
<p><b>New page</b></p><div>[[File:mini_riscv.png|1600px|right|thumb]]<br />
==Short Description==<br />
RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. Our core currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also added several instruction set extensions. A micro-controller on the other hand, does not need the full support of all the extensions. When minimal hardware costs, and ultra low power consumption is the most important requirement of a system, a micro-controller with support of only basic instructions is enough.<br />
In this project you are going to design a micro-architecture which minimizes the area footprint and power consumption in order to outperform an ARM Cortex M0.<br />
<br />
<br />
===Status: Available ===<br />
: Supervisors: [[:User:gautschi|Michael Gautschi]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Interest in Computer Architectures (RISC architectures)<br />
: VHDL/System Verilog knowledge<br />
: Programming in C<br />
<br />
===Character===<br />
: 25% Theory<br />
: 50% ASIC Design<br />
: 25% EDA tools<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
<br />
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Available]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]]</div>
Gautschi