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Minimal Cost RISC-V core

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Short Description

RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. Our core currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also added several instruction set extensions.

A simple micro-controller on the other hand, does not need the full support of all the extensions. Instead minimal hardware costs and ultra low power consumption are the most important requirements of such system. For this purpose a processor which only supports the basic instructions is enough and is thus able to achieve a higher energy-efficiency than a signal-processing optimized core.

In this project you are going to design a CPU micro-architecture which minimizes the area footprint and power consumption in order to outperform an ARM Cortex M0. The focus lies on reducing power consumption which is the most important metric. To achieve this every aspect of the design must be done with low power and minimum area in mind.


Status: Available

Supervisors: Michael Gautschi

Prerequisites

VLSI I
Interest in Computer Architectures (RISC architectures)
VHDL/System Verilog knowledge
Programming in C

Character

25% Theory
50% ASIC Design
25% EDA tools

Professor

Luca Benini

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Detailed Task Description

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Practical Details

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