View source for Neural Architecture Search using Reinforcement Learning and Search Space Reduction

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[[File:FBNet.png|400px|thumb|right|Differentiable Neural Arcitechture Search [1]]]
==Description==
Designing good and efficient neural networks is challenging, most tasks require models to be both highly accurate and robust, as well as being compact. These models then also often have constraints on energy usage, memory consumption, and latency. This results in the search space for manual design in being combinatorially large. A method of tackling the problem of manual design is instead using a neural architecture search (NAS). Many different flavors of NAS exist, such as being differentiable or DNAS [1], NAS methods that utilize evolutionary algorithms, and NAS methods that use reinforcement learning [2]. An interesting and exciting feature of NAS is the ability to include hardware constraints or have constraints on e.g., power consumption and/or memory usage guide the search process for state-of-the-art neural networks [3].


In this project, the student will explore NAS-subspaces generated using a method developed at the lab, and utilize a reinforcement learning agent to find the optimal network within these subspaces. The student will then extend the subspace generating method to datasets (NAS Spaces) that he finds and utilize RL to find the best network suited for the task at hand.

===Status: Available ===

: Supervision:[[:User:Thoriri | Thorir Mar Ingolfsson]], [[:User:Spmatteo|Matteo Spallanzani]]

===Prerequisites===
* Data science: clustering and dimensionality reduction
* Deep learning fundamentals: backpropagation, CNNs
* Programming: Python & PyTorch

===Character===
: 20% Theory
: 80% Implementation

===Literature===
* [https://arxiv.org/pdf/1812.03443.pdf] Wu et. al., FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Search
* [https://arxiv.org/pdf/1807.11626.pdf] Tan et. al., MnasNet: Platform-Aware Neural Architecture Search for Mobile
* [https://arxiv.org/pdf/1906.07214v1.pdf] Vineeth et al., Hardware Aware Neural Network Architectures (using FBNet)


===Professor===
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]
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==Detailed Task Description==

===Meetings & Presentations===
The student(s) and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. 
Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [http://eda.ee.ethz.ch/index.php/Design_review]. 
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium (as required for any semester or master thesis at D-ITET).

===Deliverables===
* description of the most promising architectures, and argumentation on the decision taken (as part of the report)
* synthesizable, verified VHDL code
* generated test vector files
* synthesis scripts & relevant software models developed for verification
* synthesis results and final chip layout (GDS II data), bonding diagram
* datasheet (part of report)
* presentation slides
* project report (in digital form; a hard copy also welcome, but not necessary)
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===Timeline==
To give some idea on how the time can be split up, we provide some possible partitioning: 
* Literature survey, building a basic understanding of the problem at hand, catch up on related work 
* Development of a working software-based implementation running on the Zynq's ARM core
* Piece-by-piece off-loading of relevant tasks to the programmable logic
* Implementation of data interfaces (software or hardware)
* Report and presentation 
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===Practical Details===
* '''[[Project Plan]]'''
* '''[[Project Meetings]]'''
* '''[[Final Report]]'''
* '''[[Final Presentation]]'''

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