Non-blocking Algorithms in Real-Time Operating Systems
- Type: Master Thesis
- Professor: Prof. Dr. L. Benini
CVA6 (formerly Ariane), 6-stage, 64-bit, in-order RISC-V core developed at IIS . It is capable of booting Linux and it is widely used both in academia and industry. The CVA 6 is currently using a basic interrupt controller (often called CLINT) to handle timer, external and software interrupts. This interrupt controller is designed for generic UNIX workloads, but fails to deliver when interrupt latency, interrupt nesting and fine grained control over interrupt priorities/levels is more critical. A new specification outlines The Core-Local Interrupt Controller (CLIC) promising low-latency, vectored, pre-emptive interrupts that tries to fill this gap.
The goal of this project is to look at data structures and task communication primitives used in FreeRTOS , an open-source real-time operating system (RTOS) used by Amazon, and determine how they use critical sections. Turn these algorithms into non-blocking versions.
We have some algorithms such as a non-blocking queue already available which can serve as a starting point. As development platform ControlPULP, a version of PULP  compromising a single RISC-V controller core and eigh RISC-V accelerator cores extended to support real-time applications, can be used. Programs can be run either on an FPGA implementation thereof or in RTL simulations.
Measure the performance impact, interrupt latency and jitter.
- 20% Literature / architecture review
- 60% Low-level C programming
- 20% Evaluation
- Strong interest in computer architecture
- Experience with low-level programming in C
- Experience with Operating Systems