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On-chip clock synthesizer design and porting

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Short Description

Mixed-signal system-on-chips (SoCs) often consist of various independent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking requirements. All-digital frequency-locked loops (ADFLLs) provide a power-efficient and easy to implement solution to individual clocking of the subsystems. ADFLLs can be entirely built from digital standard cells and integrated passive components, are easily portable between different CMOS technologies and have a small size enabling multiple instantiations, which is key to fine-grained dynamic voltage and frequency scaling (DVFS). Frequency tuning capabilities spanning the range from a few kHz up to 1 GHz and more in combination with high frequency resolution is required in SoCs targeting ultra-low power consumption. We have already built and successfully tested various generations of a low-complexity FLL design in different technologies including 65nm and 28nm CMOS technologies.

In this project, we are interested in further improving the capabilities of our current FLL design in a next generation, optimizing it toward lower area and power consumption. Moreover, an additional goal is to have an advanced FLL macro-block available for easy instantiation in any digital ASIC design developed at our institute, which requires the porting of the next-generation FLL design to other technologies.

In this project, you get the unique opportunity to do a complete mixed-signal design with a complexity that is perfect for an entry-level experience in the field. You will go through the complete digital design flow using all the standard EDA tools (same as in a digital ASIC design project), and, in addition, you will also learn to handle a simple analog design flow from circuit entry to layout. The result will be a reusable macro-block that can be used in many of your colleagues' chips instead of a single chip.

These are the topics you will deal with:

- Basic control theory
- Mixed-signal IC design
- Mixed-signal circuit simulation
- Front-end and back-end design of both analog and digital ICs

Status: Available

Looking for 1 Master student or 1 semester-project student
Supervision: David Bellasi


10% Theory
90% Hardware design


VHDL or SystemVerilog
Basic understanding of analog design and control theory


Luca Benini