Difference between revisions of "OpenRISC SoC for Sensor Applications"
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==Short Description== | ==Short Description== | ||
At the IIS we have started developing our own implementation of the OpenRISC core available from the [http://www.opencores.org Opencores] community. A brand new optimized implementation of the OpenRisc was completed as part of a [[Ultra-low power processor design | previous semester thesis]]. We are already using this core in our [[:Category:PULP|multi-core projects]] and we continue to make improvements. | At the IIS we have started developing our own implementation of the OpenRISC core available from the [http://www.opencores.org Opencores] community. A brand new optimized implementation of the OpenRisc was completed as part of a [[Ultra-low power processor design | previous semester thesis]]. We are already using this core in our [[:Category:PULP|multi-core projects]] and we continue to make improvements. |
Revision as of 15:57, 27 March 2014
Contents
Short Description
At the IIS we have started developing our own implementation of the OpenRISC core available from the Opencores community. A brand new optimized implementation of the OpenRisc was completed as part of a previous semester thesis. We are already using this core in our multi-core projects and we continue to make improvements.
We also have several projects that deal with acquiring data from sensors. We would like to expand our OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can communicate over low-power wireless channels.
- Wakeup radio
- SPI interface
- General Purpose IO
- I2C interface
The goal of the project is to make a minimal SoC that contains the OpenRISC core, sufficient memory to run example applications, the wake up radio that will listen to a wireless interface and wake-up the remaining system when necessary, and add a small set of interfaces that will allow it to connect to simple target applications in the sensing domain.
Status: Available
- Looking for 1-2 Semester/Master students
- Contact: Michael Gautschi, Michele Magno
Prerequisites
- VLSI I
- VLSI II (recommended)
Character
- 20% System Design
- 60% ASIC Design
- 20% Verification